Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFN 28

General Description

The MAX1192 is an ultra-low-power, dual, 8-bit, 22Msps

analog-to-digital converter (ADC). The device features

two fully differential wideband track-and-hold (T/H) inputs.

These inputs have a 440MHz bandwidth and accept fully

differential or single-ended signals. The MAX1192 deliv-

ers a typical signal-to-noise and distortion (SINAD) of

48.6dB at an input frequency of 5.5MHz and a sampling

rate of 22Msps while consuming only 27.3mW. This ADC

operates from a 2.7V to 3.6V analog power supply. A sep-

arate 1.8V to 3.6V supply powers the digital output driver.

In addition to ultra-low operating power, the MAX1192

features three power-down modes to conserve power

during idle periods. Excellent dynamic performance,

ultra-low power, and small size make the MAX1192 ideal

for applications in imaging, instrumentation, and digital

communications.

An internal 1.024V precision bandgap reference sets

the full-scale range of the ADC to ±0.512V. A flexible

reference structure allows the MAX1192 to use its inter-

nal reference or accept an externally applied reference

for applications requiring increased accuracy.

The MAX1192 features parallel, multiplexed, CMOS-

compatible tri-state outputs. The digital output format is

offset binary. A separate digital power input accepts a

voltage from 1.8V to 3.6V for flexible interfacing to dif-

ferent logic levels. The MAX1192 is available in a 5mm

× 5mm, 28-pin thin QFN package, and is specified for

the extended industrial (-40°C to +85°C) temperature

range.

For higher sampling frequency applications, refer to the

MAX1195–MAX1198 dual 8-bit ADCs. Pin-compatible

versions of the MAX1192 are also available. Refer to the

MAX1191 data sheet for 7.5Msps, and the MAX1193

data sheet for 45Msps.

Applications

Ultrasound and Medical Imaging

IQ Baseband Sampling

Battery-Powered Portable Instruments

Low-Power Video

WLAN, Mobile DSL, WLL Receiver

Features

o Ultra-Low Power

27.3mW (Normal Operation: 22Msps)

1.8µW (Shutdown Mode)

o Excellent Dynamic Performance

48.6dB/47.2dB SNR at f

= 5.5MHz/125MHz

70dBc/69dBc SFDR at f

= 5.5MHz/125MHz

o 2.7V to 3.6V Single Analog Supply

o 1.8V to 3.6V TTL/CMOS-Compatible Digital

Outputs

o Fully Differential or Single-Ended Analog Inputs

o Internal/External Reference Option

o Multiplexed CMOS-Compatible Tri-State Outputs

o 28-Pin Thin QFN Package

o Evaluation Kit Available (Order MAX1193EVKIT)

MAX1192

Ultra-Low-Power, 22Msps, Dual 8-Bit ADC

________________________________________________________________

Maxim Integrated Products

MAX1192

5mm x 5mm THIN QFN

TOP VIEW

PD0

EXPOSED PADDLE

PD1

REFIN

COM

REFN

REFP

INA+

INA-

GND

CLK

GND

INB+

INB-

GND

OGND

A/B

Pin Configuration

Ordering Information

19-2835; Rev 2; 7/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX1192ETI-T -40°C to +85°C 28 Thin QFN-EP*

Denotes a package containing lead(Pb).

*EP = Exposed paddle.

T = Tape and reel.

Summary of content (27 pages)

PAGE 1
9-2835; Rev 2; 7/09 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC Applications Ultrasound and Medical Imaging IQ Baseband Sampling Battery-Powered Portable Instruments Low-Power Video o Excellent Dynamic Performance 48.6dB/47.2dB SNR at fIN = 5.5MHz/125MHz 70dBc/69dBc SFDR at fIN = 5.5MHz/125MHz o 2.7V to 3.6V Single Analog Supply o 1.8V to 3.
PAGE 2
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND .................-0.3V to (VDD + 0.3V) CLK, REFIN, REFP, REFN, COM to GND ...-0.3V to (VDD + 0.3V) PD0, PD1 to OGND .................................-0.3V to (OVDD + 0.3V) Digital Outputs to OGND .........................-0.3V to (OVDD + 0.
PAGE 3
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Spurious-Free Dynamic Range (Note 2) Third-Harmonic Distortion (Note 2) SYMBOL CONDITIONS MIN fIN = 1.875MHz SFDR HD3 TYP fIN = 5.5MHz 59.0 70.0 fIN = 11MHz 70.4 fIN = 1.875MHz 75.8 fIN = 5.5MHz -74.0 fIN = 11MHz -74.
PAGE 4
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Maximum REFP/REFN/COM Sink Current SYMBOL CONDITIONS MIN ISINK TYP MAX UNITS 2 mA REFIN Input Resistance >500 kΩ REFIN Input Current -0.
PAGE 5
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD 2.7 3.0 3.6 V OVDD 1.8 VDD V POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage Analog Supply Current Normal operating mode, fIN = 1.875MHz at -0.
PAGE 6
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, fCLK = 22MHz, CREFP = CREFN = CCOM = 0.33µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS CLK Rise to CHA Output Data Valid tDOA 50% of CLK to 50% of data, Figure 5 (Note 4) 1 6 8.
PAGE 7
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) -10 -20 -40 -50 HD2 fINB HD3 -60 -70 -30 -40 -50 HD3 -60 HD2 fINA 0 -20 -70 -30 -40 -50 HD3 -70 -80 -80 -80 -90 -90 2 4 6 8 12 10 0 2 ANALOG INPUT FREQUENCY (MHz) 4 6 8 FFT PLOT CHANNEL B (DIFFERENTIAL INPUTS, 8192-POINT DATA RECORD) 0 fCLK = 22.005678MHz fINA = 8.056034MHz fINB = 5.606183MHz AINA = AINB = -0.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.
PAGE 9
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY 49.5 MAX1192 toc11 50.0 MAX1192 toc10 50.0 SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY 49.5 49.0 49.0 48.5 SINAD (dB) 48.0 47.5 48.5 CHANNEL B 48.0 47.5 CHANNEL A CHANNEL A 47.0 47.0 46.
PAGE 10
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT POWER SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER fIN = 5.512345MHz 50 fIN = 5.
PAGE 11
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. SAMPLING RATE SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE fIN = 5.512345MHz 49 SINAD (dB) 49 48 47 48 47 46 46 45 45 10 20 30 40 50 0 60 10 20 30 40 50 fCLK (MHz) fCLK (MHz) TOTAL HARMONIC DISTORTION vs.
PAGE 12
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. CLOCK DUTY CYCLE SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE fIN = 5.512345MHz 49 SINAD (dB) 49 48 47 48 47 46 46 45 45 45 50 55 40 60 TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE fIN = 5.
PAGE 13
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY 0.4 0.3 0.2 0.2 0.1 0.1 DNL (LSB) 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 32 64 96 128 160 192 224 256 32 64 128 160 192 224 256 OFFSET ERROR vs. TEMPERATURE GAIN ERROR vs.
PAGE 14
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 1.8V, VREFIN = VDD (internal reference), CL ≈ 10pF at digital outputs, differential input at -0.5dB FS, fCLK = 22.005678MHz at 50% duty cycle, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT SUPPLY CURRENT vs. INPUT FREQUENCY vs. SAMPLING RATE 25 9.8 MAX1192 toc34 MAX1192 toc33 3.0 9.6 DIGITAL SUPPLY CURRENT 2.0 9.4 1.5 9.2 1.0 9.0 ANALOG SUPPLY CURRENT 0.5 20 SUPPLY CURRENT (mA) 2.5 ANALOG SUPPLY CURRENT (mA) fIN = 5.
PAGE 15
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC PIN NAME 23 PD0 FUNCTION 24 REFIN Reference Input. Internally pulled up to VDD. 25 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 26 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. 27 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFP to GND with a 0.33µF capacitor. — EP Power-Down Digital Input 0. See Table 3. Exposed Paddle.
PAGE 16
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b COM INTERNAL BIAS HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 MAX1192 OUT INBS4b C2b C1b S3b S5b S2b INTERNAL BIAS COM Figure 3. Internal T/H Circuits Input Track-and-Hold (T/H) Circuits Figure 3 displays a simplified functional diagram of the input T/H circuits.
PAGE 17
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC VREFIN REFERENCE MODE >0.8 x VDD Internal reference mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN/2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. <0.3V Unbuffered external reference mode.
PAGE 18
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC 5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB) CHA CHB tCLK tCL tCH CLK tDOB A/B tDOA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB CHA CHB D0B D1A D1B D2A D2B D3A D3B D4A D4B D5A D5B D6A D6B tDA/B D0–D7 Figure 5. System Timing Diagram provide lowest possible jitter.
PAGE 19
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC DIFFERENTIAL INPUT VOLTAGE (IN+ - IN-) DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D7–D0) OUTPUT DECIMAL CODE 127 128 126 VREF × 128 1 VREF × 128 0 VREF × 128 1 -VREF × 128 127 -VREF × 128 +127 (+ full scale - 1 LSB) 1111 1111 255 +126 (+ full scale - 2 LSB) 1111 1110 254 +1 1000 0001 129 0 (bipolar zero) 1000 0000 128 -1 0111 1111 127 -127 (- full scale + 1 LSB) 0000 0001 1 - 128 (- full scale) 0000 0000 0 VREF × -VREF × 128 128 Table 3.
PAGE 20
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC R4 600Ω R5 600Ω MAX1192 RISO 22Ω R1 600Ω VCOM = 1V TO 1.5V VSIG = ±85mVP-P R2 300Ω R3 600Ω INACIN 5pF R6 600Ω R7 600Ω COM AV = 6V/V VCOM = VDD/2 R8 600Ω R9 600Ω RISO 22Ω CIN 5pF R10 600Ω OPERATIONAL AMPLIFIERS CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/ DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT. CONNECT THE POSITIVE SUPPLY RAIL (VCC) TO 3V. CONNECT THE NEGATIVE SUPPLY RAIL (VEE) TO GROUND. DECOUPLE VCC WITH A 0.
PAGE 21
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192 REFP 25Ω INA+ 22pF 1kΩ VIN 0.1μF 1 VIN T1 RISO 50Ω 6 INA+ MAX4108 2 5 3 4 N.C. 0.1μF 100Ω 1kΩ COM 2.2μF CIN 22pF 0.1μF COM REFN MINICIRCUITS TT1-6-KK81 0.1μF RISO 50Ω 25Ω INA- INA- 100Ω CIN 22pF 22pF MAX1192 REFP 25Ω MAX1192 INB+ 22pF VIN 0.1μF 1 VIN N.C. T1 0.1μF 1kΩ RISO 50Ω 6 INB+ MAX4108 2 5 3 4 100Ω 2.2μF 1kΩ CIN 22pF 0.1μF REFN MINICIRCUITS TT1-6-KK81 0.1μF RISO 50Ω 25Ω INB22pF Figure 8.
PAGE 22
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC 3V 24 0.1μF 1.248V VDD REFIN 0.1μF 1 2 27 MAX6061 3 10Hz LOWPASS FILTER REFP N=1 0.33μF 1% 20kΩ MAX1192 26 REFN 0.33μF 1% 90.9kΩ 1μF 25 3V 3 NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES ±15mA OF OUTPUT DRIVE AND SUPPORTS OVER 1000 MAX1192s. 5 GND 0.1μF 1 4 COM 0.33μF 15Ω 1.023V MAX4250 2 24 VDD REFIN 0.1μF 2.2μF 0.1μF 27 REFP N = 1000 0.33μF MAX1192 26 REFN 0.33μF 25 COM 0.33μF GND Figure 10.
PAGE 23
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC MAX1192 3V 2.500V 1 0.1μF 2 27 MAX6066 1% 30.1kΩ 3 3 10μF 6V 0.1μF 12 1MΩ 13 14 MAX4254 1.47kΩ 10μF 6V 24 COM GND 0.33μF 0.1μF 27 330μF 6V 1.47kΩ VDD REFP N = 160 0.33μF 47Ω 8 MAX4254 10μF 6V 2.2μF 1.47kΩ 1.248V 1/4 11 25 330μF 6V 10 9 REFIN 47Ω 7 1% 10.0kΩ 4 1/4 330μF 6V MAX4254 3V UNCOMMITTED MAX1192 1.498V 1/4 1MΩ REFN 0.33μF 1% 10.
PAGE 24
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC A/B MAX2451 INA+ INA0° 90° MAX1192 DSP POSTPROCESSING INB+ INBDOWNCONVERTER ÷8 Figure 12. Typical QAM Receiver Application Typical QAM Demodulation Application Quadrature amplitude modulation (QAM) is frequently used in digital communications. Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase.
PAGE 25
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC Aperture Jitter CLK Figure 13 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. ANALOG INPUT Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 13). tAD tAJ SAMPLED DATA (T/H) T/H Signal-to-Noise Ratio (SNR) TRACK HOLD TRACK Figure 13.
PAGE 26
MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC Total Harmonic Distortion (THD) Third-Order Intermodulation (IM3) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: IM3 is the power of the worst third-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The third-order intermodulation products are (2 x f1 ±f2), (2 x f2 ±f1).
PAGE 27
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC REVISION NUMBER REVISION DATE 2 7/09 DESCRIPTION Changed orientation of Maxim logo in Pin Configuration diagram PAGES CHANGED 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.