Datasheet

MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
20 ______________________________________________________________________________________
In idle mode, the pipeline ADCs, reference, and clock
distribution circuits are powered, but the outputs are
forced to tri-state. The wake-up time from idle mode is
dominated by the 5ns required for the output drivers to
start from tri-state. When the outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs.
In the normal operating mode, all sections of the
MAX1192 are powered.
Applications Information
The circuit of Figure 7 operates from a single 3V supply
and accommodates a wide 0.5V to 1.5V input common-
mode voltage range for the analog interface between
an RF quadrature demodulator (differential, DC-cou-
pled signal source) and a high-speed ADC.
Furthermore, the circuit provides required SINAD and
SFDR to demodulate a wideband (BW = 3.84MHz),
QAM-16 communication link. R
ISO
isolates the op amp
output from the ADC capacitive input to prevent ringing
and oscillation. C
IN
filters high-frequency noise.
MAX1192
INA+
COM
INA-
A
V
= 6V/V
V
COM
= V
DD
/2
V
COM
= 1V TO 1.5V
V
SIG
= ±85mV
P-P

R
ISO
22Ω
R
ISO
22Ω
R11
600Ω
R9
600Ω
R2
300Ω
OPERATIONAL AMPLIFIERS
CHOOSE EITHER OF THE MAX4452/MAX4453/MAX4454 SINGLE/
DUAL/QUAD +3V, 200MHz OP AMPS FOR USE WITH THIS CIRCUIT.
CONNECT THE POSITIVE SUPPLY RAIL (V
CC
) TO 3V. CONNECT THE
NEGATIVE SUPPLY RAIL (V
EE
) TO GROUND. DECOUPLE V
CC
WITH A
0.1μF CAPACITOR TO GROUND.
RESISTOR NETWORKS
RESISTOR NETWORKS ENSURE PROPER THERMAL AND TOLERANCE
MATCHING. FOR R1, R2, AND R3 USE A NETWORK SUCH AS VISHAY'S
3R MODEL NUMBER 300192. FOR R4–R11, USE A NETWORK SUCH AS
VISHAY'S 4R MODEL NUMBER 300197.
R10
600Ω
R8
600Ω
R5
600Ω
R4
600Ω
R7
600Ω
R6
600Ω
C
IN
5pF
C
IN
5pF

R1
600Ω
R3
600Ω
Figure 7. DC-Coupled Differential Input Driver