Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal PDIP 24

General Description

The MAX120/MAX122 complete, BiCMOS, sampling 12-bit

analog-to-digital converters (ADCs) combine an on-chip

track/hold (T/H) and a low-drift voltage reference with fast

conversion speeds and low-power consumption. The T/H’s

350ns acquisition time combined with the MAX120’s 1.6µs

conversion time results in throughput rates as high as 500k

samples per second (ksps). Throughput rates of 333ksps

are possible with the 2.6µs conversion time of the MAX122.

The MAX120/MAX122 accept analog input voltages from

-5V to +5V. The only external components needed are

decoupling capacitors for the power-supply and refer-

ence voltages. The MAX120 operates with clocks in the

0.1MHz to 8MHz frequency range. The MAX122 accepts

0.1MHz to 5MHz clock frequencies.

The MAX120/MAX122 employ a standard microprocessor

(µP) interface. Three-state data outputs are configured

to operate with 12-bit data buses. Data-access and bus-

release timing specifications are compatible with most

popular µPs without resorting to wait states. In addition,

the MAX120/MAX122 can interface directly to a first-in,

first-out (FIFO) buffer, virtually eliminating µP interrupt

overhead. All logic inputs and outputs are TTL/CMOS

compatible. For applications requiring a serial interface,

refer to the MAX121.

Applications

● Digital-Signal Processing

● Audio and Telecom Processing

● Speech Recognition and Synthesis

● High-Speed Data Acquisition

● Spectrum Analysis

● Data Logging Systems

Features

● 12-Bit Resolution

● No Missing Codes Over Temperature

● 20ppm/°C—5V Internal Reference

● 1.6µs Conversion Time/500ksps Throughput

(MAX120)

● 2.6µs Conversion Time/333ksps Throughput

(MAX122)

● Low Noise and Distortion:

• 70dB (min) SINAD

• -77dB (max) THD (MAX122)

● Low Power Dissipation: 210mW

● Separate Track/Hold Control Input

● Continuous-Conversion Mode Available

● ±5V Input Range, Overvoltage Tolerant to ±15V

● 24-Pin Narrow DIP, Wide SO, and SSOP Packages

19-0030; Rev 1; 3/12

+Denotes a lead(Pb)-free/RoHS-compliant package.

PART TEMP RANGE

PIN-

PACKAGE

INL

(LSB)

MAX120CNG+ 0°C to +70°C 24 PDIP ±1

MAX120CWG+ 0°C to +70°C 24 Wide SO ±1

MAX120CAG+ 0°C to +70°C 24 SSOP ±1

MAX120ENG+ -40°C to +85°C 24 PDIP ±1

MAX120EWG+ -40°C to +85°C 24 Wide SO ±1

AIN CLKIN

MODE

INT/BUSY

PDIP/SO/SSOP

TOP VIEW

D11

D10 D2

REF

AGND D0

CONVST

D9 D39 16

D8 D4

10 15

D7 D5

11 14

DGND D6

12 13

MAX120

MAX122

MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold

and Reference

Pin Conguration

Functional Diagram

Ordering Information

Summary of content (15 pages)

PAGE 1
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference General Description The MAX120/MAX122 complete, BiCMOS, sampling 12-bit analog-to-digital converters (ADCs) combine an on-chip track/hold (T/H) and a low-drift voltage reference with fast conversion speeds and low-power consumption. The T/H’s 350ns acquisition time combined with the MAX120’s 1.6µs conversion time results in throughput rates as high as 500k samples per second (ksps). Throughput rates of 333ksps are possible with the 2.
PAGE 2
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Absolute Maximum Ratings VDD to DGND...........................................................-0.3V to +6V VSS to DGND.........................................................+0.3V to -17V AIN to AGND........................................................................±15V AGND to DGND..................................................................±0.3V Digital Inputs/Outputs to DGND.....................-0.3V to (V + 0.
PAGE 3
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Electrical Characteristics (continued) (VDD = +4.75V to +5.25V, VSS = -10.8V to -15.75V, fCLK = 8MHz for MAX120 and 5MHz for MAX122, TA = TMIN to TMAX, unless otherwise noted.
PAGE 4
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Timing Characteristics (VDD = +5V, VSS = -12V to -15V, 100% tested, TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Pin Description (continued) PIN NAME FUNCTION 6 AGND 7–11, 13–19 D11–D0 Analog Ground 12 DGND 20 CONVST 21 CLKIN 22 INT/BUSY 23 CS Chip-Select Input, Active-Low. When RD is low, enables the three-state outputs. If CONVST and RD are low, a conversion is initiated on the falling edge of CS. 24 RD Read Input, Active-Low. When CS is low, RD enables the three-state outputs.
PAGE 6
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 3. MAX120/MAX122 in the Simplest Operational Mode (Continuous Conversion) Figure 4. Equivalent Input Circuit Internal Reference Digital Interlace The MAX120/MAX122 -5.00V buried-zener reference biases the internal DAC. The reference output is available at the VREF pin and must be bypassed to the AGND pin with a 0.1µF ceramic capacitor in parallel with a 22µF or greater electrolytic capacitor.
PAGE 7
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 5. Clock and Control Synchronization Figure 7. Full-Control Mode (Mode 1) or for µP-based systems where the ADC and the µP are linked through first-in, first-out (FIFO) buffers or direct memory access (DMA) ports. Slow-memory mode (mode 3) is intended for µPs that can be forced into a wait state during the ADC’s conversion time. ROM mode (mode 4) is for µPs that cannot be forced into a wait state. Figure 6.
PAGE 8
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 8. Stand-Alone Mode (Mode 2) Figure 9. Slow-Memory Mode (Mode 3) Initialization After Power-Up When the conversion is complete, the data can be read without initiating a new conversion by pulling RD and CS low and leaving CONVST high. To start a new conversion without reading data, RD and CS should remain high while CONVST is driven low.
PAGE 9
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 12. Conversion-Control Logic Figure 10. ROM Mode (Mode 4) continuously at the rate of one conversion for every 14 clock cycles, which includes 2 clock cycles for the T/H acquisition time. To satisfy the 350ns minimum acquisition time requirement within 2 clock cycles, the MAX120’s maximum clock frequency is 6MHz when operating in mode 5.
PAGE 10
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 13. Using MAX120 with FIFO Memory Digital-Bus Noise If the ADC’s data bus is active during a conversion, coupling from the data pins to the ADC comparator can cause errors. Using slow-memory mode (mode 3) avoids this problem by placing the µP in a wait state during the conversion. If the data bus is active during the conversion in either mode 1 or 4, use three-state drivers to isolate the bus from the ADC.
PAGE 11
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 16. VDD Power-Supply Rejection vs. Frequency Figure 14. Power-Supply Grounding To adjust bipolar offset with Figure 19’s circuit, apply +1/2 LSB (0.61mV) to the noninverting amplifier input and adjust R4 for output-code flicker between 0000 and 0000 0000 0001. For full scale, apply FS - the output code flickers between 0111 1111 1110 and 0111 1111 1111. There may be some interaction between these adjustments.
PAGE 12
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 17. Bipolar Transfer Function Figure 19. Offset and Gain Adjustment (Noninverting) Figure 18. Trim Circuit for Gain Only Figure 19. Offset and Gain Adjustment (Noninverting) ADCs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (INL), and differential nonlinearity (DNL).
PAGE 13
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Figure 21. Inverting Bipolar Transfer Function Figure 23. Effective Bits vs. Input Frequency where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. The THD specification in the Electrical Characteristics table includes the 2nd through 5th harmonics.
PAGE 14
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Spurious-Free Dynamic Range Spurious-free dynamic range is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually the next largest spectral component occurs at some harmonic of the input frequency. However, if the ADC is exceptionally linear, it may occur only at a random peak in the ADC’s noise floor.
PAGE 15
MAX120/MAX122 500ksps, 12-Bit ADCs with Track/Hold and Reference Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 9/92 Initial release 1 3/12 Removed PDIP, CERDIP packages from Ordering Information. Updated style throughout data sheet. DESCRIPTION — 1–16 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.