9-3295; Rev 7; 2/12 KIT ATION EVALU LE B A IL A AV 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Features The MAX1220/MAX1257/MAX1258 integrate a 12-bit, multichannel, analog-to-digital converter (ADC), and a 12bit, octal, digital-to-analog converter (DAC) in a single IC. These devices also include a temperature sensor and configurable general-purpose I/O ports (GPIOs) with a 25MHz SPI-/QSPI™-/MICROWIRE®-compatible serial interface.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V DVDD to AVDD......................................................-3.0V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND ........................-0.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C. Outputs are unloaded, unless otherwise noted.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C. Outputs are unloaded, unless otherwise noted.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C. Outputs are unloaded, unless otherwise noted.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD (MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ANALOG SHUTDOWN CURRENT vs. ANALOG SUPPLY VOLTAGE 0.3 0.2 0.1 0.4 0.3 0.2 0.1 MAX1220/MAX1258 0 4.875 5.000 5.125 0.1 MAX1257 0 2.7 3.0 3.3 3.6 -40 -15 10 35 60 TEMPERATURE (°C) ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE ADC INTEGRAL NONLINEARITY vs. OUTPUT CODE ADC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0 -0.25 -0.50 0.25 0 -0.25 -0.50 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -0.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) ADC GAIN ERROR ADC GAIN ERROR ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE vs. ANALOG SUPPLY VOLTAGE vs. TEMPERATURE MAX1257 0 -0.5 -0.5 -2 MAX1220/MAX1258 -1.0 4.750 4.875 5.000 -1.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 0 -0.5 -1.0 0.5 0 -0.5 -1.0 MAX1220/MAX1258 2048 3072 1024 0 2048 3072 2047 4096 2053 2056 2059 DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE DAC FULL-SCALE ERROR vs. ANALOG SUPPLY VOLTAGE 0.8 0.6 0.4 0.8 0.6 0.4 MAX1257 EXTERNAL REFERENCE = 2.5V 0.2 0.2 2050 1.0 MAX1220/MAX1258 EXTERNAL REFERENCE = 4.096V -0.4 2053 2056 2059 4.750 2062 4.875 5.000 5.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE -3 -4 -5 -5 -10 MAX1220 toc30 MAX1220 toc29 0 5 DAC FULL-SCALE ERROR (LSB) -2 5 DAC FULL-SCALE ERROR (LSB) -1 DAC FULL-SCALE ERROR vs.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports -40 -100 -80 -100 -120 -120 -140 -140 -140 -160 50 100 150 200 150 200 50 0 100 150 ANALOG INPUT FREQUENCY (kHz) DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT GPIO OUTPUT VOLTAGE vs. SOURCE CURRENT DAC OUTPUT VOLTAGE (V) 2.05 2.04 SINKING SOURCING 2.02 1.28 1.27 1.26 1.25 1.24 SINKING 1.23 SOURCING 1.22 DAC OUTPUT = MIDSCALE MAX1220/MAX1258 2.
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) DAC-TO-DAC CROSSTALK DAC-TO-DAC CROSSTALK TEMPERATURE SENSOR ERROR RLOAD = 10kΩ, CLOAD = 100pF RLOAD = 10kΩ, CLOAD = 100pF vs. TEMPERATURE MAX1220 toc48 MAX1220 toc47 MAX1220 toc46 1.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ, CLOAD = 100pF, CS = HIGH, DIN = LOW MAX1220 toc56 MAX1220 toc55 NEGATIVE FULL-SCALE SETTLING TIME RLOAD = 10kΩ, CLOAD = 100pF MAX1220 toc57 MAX1257 SCLK 2V/div SCLK 1V/div VOUT_ 1V/div VOUT_ 100mV/div AC-COUPLED VOUT_ 100mV/div AC-COUPLED VLDAC 1V/div MAX1220/MAX1258 MAX1257 200ns/div 200ns/div 1µs/div NEG
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description PIN NAME FUNCTION MAX1220 MAX1257 MAX1258 1, 2 — 3 4 EOC 4 7 DVDD Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor. 5 8 DGND Digital Ground. Connect DGND to AGND. 6 9 DOUT Serial-Data Output. Data is clocked out on the falling edge of the SCLK clock in modes 00, 01, and 10. Data is clocked out on the rising edge of the SCLK clock in mode 11.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports PIN MAX1220 MAX1257 MAX1258 NAME FUNCTION Reference 1 Input. Reference voltage; leave unconnected to use the internal reference (2.5V for the MAX1257 or 4.096V for the MAX1220/MAX1258). REF1 is the positive reference in ADC external differential reference mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Detailed Description The MAX1220/MAX1257/MAX1258 integrate a 12-bit, multichannel, analog-to-digital converter (ADC), and a 12-bit, octal, digital-to-analog converter (DAC) in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI-/QSPI-/MICROWIRE-compatible serial interface. The ADC is available in 8 and 16 input-channel versions.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports USER-PROGRAMMABLE I/O MAX1220/MAX1257/MAX1258 AVDD GPIOA0– GPIOB0– GPIOC0– GPIOA3 GPIOB3 GPIOC3 DVDD MAX1257 MAX1258 GPIO CONTROL OSCILLATOR INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT0 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT1 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT2 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUT
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 1. Command Byte (MSB First) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDITIONAL NO.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar or Bipolar Conversions Address the unipolar- and bipolar-mode registers through the setup register (bits 1 and 0). See Table 5 for the setup register. See Figures 3 and 4 for the transferfunction graphs. Program a pair of analog inputs for differential operation by writing a one to the appropriate bit of the bipolar- or unipolar-mode register. Unipolar mode sets the differential input range from 0 to VREF1.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports The first 2 bytes of data read out after a temperature measurement always contain the 12-bit temperature result, preceded by four leading zeros, MSB first. If another temperature measurement is performed before the first temperature result is read out, the old measurement is overwritten by the new result. Temperature results are in degrees Celsius (two’s complement), at a resolution of 8 LSB per degree.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports The GPIOs can sink and source current. The MAX1257/MAX1258 GPIOA0–GPIOA3 can sink and source up to 15mA. GPIOB0–GPIOB3 and GPIOC0– GPIOC3 can sink 4mA and source 2mA. The MAX1220 GPIOA0 and GPIOA1 can sink and source up to 15mA. The MAX1220 GPIOC0 and GPIOC1 can sink 4mA and source 2mA. See Table 3. Clock Modes Internal Clock The MAX1220/MAX1257/MAX1258 can operate from an internal oscillator.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports names. Tables 4–12 show the various functions within the conversion register, setup register, unipolar-mode register, bipolar-mode register, ADC averaging register, DAC select register, reset register, and GPIO command register, respectively.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT — 7 (MSB) Set to zero to select setup register. FUNCTION — 6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference-mode configuration. REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports The ADC reference is always on if any of the following conditions are true: 3) At least one DAC is powered down through the 100kΩ to VREF and REFSEL[1:0] = 00. 1) The FBGON bit is set to one in the reset register. 2) At least one DAC output is powered up and REFSEL[1:0] (in the setup register) = 00.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. FUNCTION UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Configure AIN8 and AIN9 for unipolar differential conversion.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Select Register Write a command byte 0001XXXX to the DAC select register (as shown in Table 10) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command Table 10. DAC Select Register BIT NAME — BIT FUNCTION byte controls the DAC serial interface.
GPIO Command Write a command byte to the GPIO command register to configure, write, or read the GPIOs, as detailed in Table 12. Write the command byte 00000011 to configure the GPIOs. The eight SCLK cycles following the command byte load data from DIN to the GPIO configuration register in the MAX1220. The 16 SCLK cycles following the command byte load data from DIN to the GPIO configu- ration register in the MAX1257/MAX1258. See Tables 13 and 14. The register bits are updated after the last CS rising edge.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports GPIO Read Write the command byte 00000001 to indicate a GPIO read operation. The eight SCLK cycles following the command byte transfer the state of the GPIOs to DOUT in the MAX1220. The 16 SCLK cycles following the command byte transfer the state of the GPIOs to DOUT in the MAX1257/MAX1258. See Tables 18 and 19.
Table 20. DAC Serial-Interface Configuration 16-BIT SERIAL WORD MSB LSB CONTROL BITS DESCRIPTION DATA BITS FUNCTION C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 X X X X X X X X X X X X NOP No operation. X X X X X X X X X RESET 0 0 0 1 1 X 1 X X X X X X X X X Pull-High Preset all internal registers to FFFh and leave output buffers in their present state.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CONTROL BITS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 C3 C2 C1 C0 DATA BITS DESCRIPTION FUNCTION D3 D2 D1 D0 — — — — — — — — 0 — — — — — — — — 0 — — — — — — — — 1 — — — — — — — — 0 — — — — — — — — 1 0 1 0 0 1 1 0 0 0 1 X Power-Up Power up individual DAC buffers indicated by data in DAC0 through DAC7.
Partial Reads and Partial Writes If the 1st byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the remaining bits are lost for that byte. The next byte of data that is read out contains the next 8 bits. If the first byte of an entry in the FIFO is read out fully, but the second byte is read out partially, the rest of that byte is lost.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1220/MAX1257/MAX1258 CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 tRDS EOC Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion. tCSW CNVST (CONVERSION 2) (ACQUISITION 1) (ACQUISITION 2) CS tDOV SCLK (CONVERSION 1) DOUT MSB1 LSB1 MSB2 EOC Figure 7.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CONVERSION BYTE DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT tDOV MSB1 LSB1 MSB2 EOC Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required). Set CNVST high to begin a conversion. Sampling is completed approximately 500ns after CNVST goes high.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports NOP CONVERSION BYTE #2 NOP CONVERSION ACQUISITION #1 CONVERSION #1 ACQUISITION #2 CONVERSION #2 CS SCLK DOUT MSB1 LSB1 MSB2 EOC Figure 9a. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST for Maximum ADC Throughput CONVERSION BYTE NOP NOP DIN ACQUISITION CONVERSION CS SCLK DOUT MSB1 LSB1 EOC Figure 9b.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports tCL SCLK 1 tDS 2 3 Dn-3 Dn-2 Dn-4 Dn-5 D1 D0 tDOT tDOE D15 D7 DOUT 32 16 8 5 4 tDH Dn-1 DIN tCH D14 D6 D13 D5 tDOD D12 D4 D1 D0 tCSS tCSPWH tCSH CS NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24. Figure 10.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1220/MAX1257/MAX1258 tCH tCL SCLK 1 2 3 32 16 8 5 4 tDH tDS Dn-1 DIN Dn-2 Dn-3 Dn-4 D1 Dn-5 D0 tDOT tDOE D15 D7 DOUT D14 D6 tDOD D13 D5 D12 D4 D1 D0 tCSS tCSPWH tCSH CS NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24. Figure 11.
MAX1220/MAX1257/MAX1258 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CS tGOD tGSU GPIO INPUT/OUTPUT Figure 13. GPIO Timing tLDACPWL LDAC tS ±1 LSB OUT_ Figure 14. LDAC Functionality LDAC Functionality Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently low to make the DAC register transparent. The DAC output typically settles from zero to full scale within ±1 LSB after 2µs. See Figure 14.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD(dB) = 20 x log (SignalRMS / NoiseRMS) Bipolar ADC Offset Error While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports OUT7 16 17 18 OUT5 OUT6 15 N.C.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports REVISION REVISION NUMBER DATE 5 12/07 DESCRIPTION Changed timing characteristic specification. 7 Changed the Ordering Information table to show lead(Pb)-free packages. 1 Added Note 18 to the Electrical Characteristics table (tDOV spec). 6 1/10 Added the ADDITIONAL NO. OF BYTES column to Table 1. Corrected Figure 8, replaced Figure 9 with Figures 9a and 9b, and modified Figures 10 and 11.