9-4010; Rev 1; 12/07 KIT ATION EVALU E L B A IL AVA 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Features ♦ 12-Bit, 225ksps ADC Analog Multiplexer with True-Differential Track/Hold (T/H) 12 Single-Ended Channels or Six Differential Channels (Unipolar or Bipolar) (MAX1223) Eight Single-Ended Channels or Four Differential Channels (Unipolar or Bipolar) (MAX1221/MAX1343) Excellent Accuracy: ±0.5 LSB INL, ±0.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ABSOLUTE MAXIMUM RATINGS AVDD to AGND .........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V DVDD to AVDD .......................................................-3.0V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND .........................-0.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER Acquisition Time SYMBOL tACQ Conversion Time tCONV External-Clock Frequency fCLK CONDITIONS (Note 5) MIN TYP MAX 0.6 Internally clocked µs 5.5 µs Externally clocked 3.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL REF1 Input Current (Note 9) IREF1 REF2 Input Current IREF2 CONDITIONS MIN TYP MAX UNITS VREF = 2.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS From power-down mode, AVDD = 5V 25 From power-down mode, AVDD = 2.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) PARAMETER ADC Positive-Supply Rejection SYMBOL PSRA CONDITIONS MIN Full-scale input, AVDD = 2.7V to 5.25V TYP MAX UNITS ±0.06 ±0.
ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at AVDD = DVDD = 3V. TA = +25°C. Outputs are unloaded, unless otherwise noted.) Note 1: Tested at DVDD = AVDD = +2.7V. Note 2: Offset nulled. Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles, multiplied by the clock period.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 0.50 0.25 0 -0.25 -0.50 -0.75 0.75 0.50 0.25 0 -0.25 -0.50 1.00 1024 2048 4096 3072 0 -0.25 -0.50 0 1024 2048 3072 0 4096 1024 2048 4096 3072 OUTPUT CODE OUTPUT CODE ADC OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE ADC OFFSET ERROR vs. TEMPERATURE ADC GAIN ERROR vs. ANALOG SUPPLY VOLTAGE 0.4 1 0.5 GAIN ERROR (LSB) OFFSET ERROR (LSB) 0.6 1.0 0 -1 -2 3.0 3.5 4.0 4.5 5.0 -1.0 -40 5.5 0 -0.5 0.
Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) 1.98 1.96 1.94 1.92 1.96 MAX1221 toc14 AVDD = DVDD = 3V 1.94 1.92 3.0 3.5 4.0 4.5 5.0 5.5 0.5 0 -0.5 -1.5 1.88 -40 -15 10 35 60 0 85 3072 OUTPUT CODE DAC INTEGRAL NONLINEARITY vs. OUTPUT CODE DAC DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE DAC DIFFERENTIAL NONLINEARITY vs.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC FULL-SCALE ERROR vs. REFERENCE VOLTAGE 0.50 0.25 0 -0.25 -0.50 -3 -4 -5 MAX1221 toc24 0 -5 -10 -15 -7 1 2 3 4 5 0.5 0 1.0 1.5 2.0 2.5 0 3.0 15 20 DAC FULL-SCALE ERROR vs. LOAD CURRENT INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE ADC REFERENCE SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE 2.51 2.50 2.49 2.48 -15 0.5 1.0 1.5 2.0 2.
Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.) -40 -20 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 100 200 150 50 100 2.02 SINKING SOURCING DAC OUTPUT = MIDSCALE -30 0 1.26 1.25 SINKING SOURCING MAX1221 toc35 5 GPIO OUTPUT VOLTAGE (V) 1.27 1.23 30 4 GPIOA0, AGPIOA1 OUTPUTS 3 2 GPIOC0, GPIOC1 OUTPUTS 1 1.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports GPIO OUTPUT VOLTAGE vs. SINK CURRENT TEMPERATURE SENSOR ERROR vs. TEMPERATURE 1200 900 600 GPIOA0, GPIOA1 OUTPUTS 300 1.00 MAX1221 toc39 GPIOC0, GPIOC1 OUTPUTS TEMPERATURE SENSOR ERROR (°C) MAX1221 toc38 GPIO OUTPUT VOLTAGE (mV) 1500 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Typical Operating Characteristics (continued) (AVDD = DVDD = 3V external VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF, TA = +25°C, unless otherwise noted.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports NEGATIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) NEGATIVE FULL-SCALE SETTLING TIME (RLOAD = 10kΩ, CLOAD = 100pF) MAX1221 toc51 MAX1340 toc50 VLDAC 2V/div VOUT 1V/div VOUT_ 2V/div VLDAC 1V/div AVDD = DVDD = 5V EXTERNAL REFERENCE = 4.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Pin Description PIN NAME FUNCTION MAX1221 MAX1223 MAX1343 1, 2 — 1, 2 GPIOA0, GPIOA1 — 1 — CNVST/AIN11 3 3 3 EOC Active-Low End-of-Conversion Output. Data is valid after the falling edge of EOC. 4 4 4 DVDD Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF capacitor. 5 5 5 DGND Digital Ground. Connect DGND to AGND. 6 6 6 DOUT Serial-Data Output.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports PIN MAX1221 MAX1223 MAX1343 — 23, 25, 27–31, 33, 34, 35 — NAME AIN0–AIN9 FUNCTION Analog Inputs Reference 1 Input. Reference voltage; leave unconnected to use the internal reference (2.5V). REF1 is the positive reference in ADC differential mode. Bypass REF1 to AGND with a 0.1µF capacitor in external reference mode only. See the ADC/DAC References section.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Detailed Description The MAX1221/MAX1223/MAX1343 integrate a multichannel 12-bit ADC, and an octal/quad 12-bit DAC in a single IC. The devices also include a temperature sensor and configurable GPIOs with a 25MHz SPI-/QSPI-/ MICROWIRE-compatible serial interface. The ADC is available in a 12 or an eight input-channel version. The DAC outputs settle within 2.0µs, and the ADC has a 225ksps conversion rate.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 AVDD GPIOC0, GPIOC1 GPIOA0, GPIOA1 DVDD MAX1221 USER-PROGRAMMABLE I/O GPIO CONTROL OSCILLATOR INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT0 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT1 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT2 INPUT REGISTER DAC REGISTER 12-BIT DAC BUFFER OUTPUT CONDITIONING OUT3
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 1.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Analog Input (T/H) The equivalent circuit of Figure 2 shows the ADC input architecture of the MAX1223. In track mode, a positive input capacitor is connected to AIN0–AIN11 in singleended mode and AIN0, AIN2, AIN4–AIN10 in differential mode. A negative input capacitor is connected to AGND in single-ended mode or AIN1, AIN3, AIN5–AIN11 in differential mode. The MAX1221/MAX1343 feature eight analog input channels (AIN0–AIN7).
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports LSB per degree. See the Temperature Measurements section for details on converting the digital code to a temperature. 12-Bit DAC In addition to the 12-bit ADC, the MAX1221/MAX1223/ MAX1343 also include eight (MAX1221/MAX1223) or four (MAX1343) voltage-output, 12-bit, monotonic DACs with less than 4 LSB integral nonlinearity error and less than 1 LSB differential nonlinearity error.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Internal Clock The MAX1221/MAX1223/MAX1343 can operate from an internal oscillator. The internal oscillator is active in clock modes 00, 01, and 10. Figures 6, 7, and 8 show how to start an ADC conversion in the three internally timed conversion modes. Read out the data at clock speeds up to 25MHz through the SPI interface.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Channels 8–11 are invalid. Any scans or averages on these channles can cause corrupt data. Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the selected scanning range (set by bits 2 and 1, SCAN1 and SCAN0), plus one temperature result if selected.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT FUNCTION — 7 (MSB) Set to zero to select setup register. — 6 Set to one to select setup register. CKSEL1 5 Clock mode and CNVST configuration; resets to one at power-up. CKSEL0 4 Clock mode and CNVST configuration. REFSEL1 3 Reference-mode configuration. REFSEL0 2 Reference-mode configuration. DIFFSEL1 1 Unipolar-/bipolar-mode register configuration for differential mode.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Table 5c. Clock Mode 11 REFSEL1 REFSEL0 0 0 VOLTAGE REFERENCE OVERRIDE CONDITIONS AIN Internal reference turns off after scan is complete. If internal reference is turned off, there is a programmed delay of 218 external-conversion clock cycles. Temperature Internal reference required. There is a programmed delay of 244 external-conversion clock cycles for the internal reference.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports BIT NAME BIT FUNCTION UCH0/1 7 (MSB) Configure AIN0 and AIN1 for unipolar differential conversion. UCH2/3 6 Configure AIN2 and AIN3 for unipolar differential conversion. UCH4/5 5 Configure AIN4 and AIN5 for unipolar differential conversion. UCH6/7 4 Configure AIN6 and AIN7 for unipolar differential conversion. UCH8/9 3 Configure AIN8 and AIN9 for unipolar differential conversion (MAX1223).
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Unipolar/Bipolar Registers The final 2 bits (LSBs) of the setup register control the unipolar-/bipolar-mode address registers. Set DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte must be followed by 1 byte of data that is written to the unipolar-mode register or bipolar-mode register.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DAC Select Register Write a command byte 0001XXXX to the DAC select register (as shown in Table 9) to set up the DAC interface and indicate that another word will follow. The last 4 bits of the DAC select register are don’t-care bits. The word that follows the DAC select-register command Table 10. DAC Select Register BIT NAME — BIT FUNCTION 6 Set to zero to select DAC select register.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports GPIO Command Write a command byte to the GPIO command register to configure, write, or read the GPIOs, as detailed in Table 12. Write the command byte 00000011 to configure the GPIOs. The eight SCLK cycles following the command byte load data from DIN to the GPIO configuration register in the MAX1221/MAX1343. See Tables 13 and 14. The register bits are updated after the last CS rising edge.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 16-BIT SERIAL WORD MSB LSB CONTROL BITS DATA BITS DESCRIPTION FUNCTION C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 X X X X X X X X X X X X NOP 0 0 0 1 0 X X X X X X X X X X X RESET 0 0 0 1 1 X X X X X X X X X X X Pull-High 0 0 1 0 — — — — — — — — — — — — DAC0 D11–D0 to input register 0, DAC output unchanged.
Table 17. DAC Serial-Interface Configuration (continued) 16-BIT SERIAL WORD MSB LSB CONTROL BITS DATA BITS C3 C2 C1 C0 D11 D10 D9 1 1 1 1 0 1 1 0 — — — D8 — D7 D6 — — D5 — D4 D3 — — DAC DAC DAC DAC DAC DAC DAC DAC X 7 6 5 4 3 2 1 0 D2 — X D1 — X DESCRIPTION FUNCTION DAC0–7 D11–D0 to input registers 0–7 (MAX1221/MAX1223). D11–D0 to input registers 0–3 (MAX1343). DAC outputs unchanged.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Output-Data Format Figures 6–9 illustrate the conversion timing for the MAX1221/MAX1223/MAX1343. All 12-bit conversion results are output in 2-byte format, MSB first, with four leading zeros. Data appears on DOUT on the falling edges of SCLK. Data is binary for unipolar mode and two’s complement for bipolar mode and temperature results. See Figures 3, 4, and 5 for input/output and temperature-transfer functions.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 tRDS EOC Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion. tCSW CNVST (CONVERSION 2) (ACQUISITION 1) (ACQUISITION 2) CS tDOV SCLK (CONVERSION 1) DOUT MSB1 LSB1 MSB2 EOC Figure 7.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports (CONVERSION BYTE) (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 tDOV LSB1 MSB2 EOC Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports DIN (CONVERSION BYTE) (CONVERSION1) (ACQUISITION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC Figure 9.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports SCLK 1 tDS 2 tCH 3 D13 D14 D12 D11 D1 D0 tDOT tDOE D15 D7 DOUT 32 16 8 5 4 tDH D15 DIN MAX1221/MAX1223/MAX1343 tCL D14 D6 D13 D5 tDOD D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 10.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports tCH tCL SCLK 1 2 3 32 16 8 5 4 tDH tDS D15 DIN D14 D13 D12 D11 D1 D0 tDOT tDOE D15 D7 DOUT D14 D6 tDOD D13 D5 D12 D4 D1 D0 tCSS tCSPWH tCSH CS Figure 11.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports MAX1221/MAX1223/MAX1343 CS tGOD tGSU GPIO INPUT/OUTPUT Figure 13. GPIO Timing tLDACPWL LDAC tS ±1 LSB OUT_ Figure 14. LDAC Functionality Layout, Grounding, and Bypassing For best performance, use PC boards. Ensure that digital and analog signal lines are separated from each other.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Bipolar ADC Offset Error Effective Number of Bits While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the measured deviation from this ideal value. Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Chip Information TRANSISTOR COUNT: 58,141 PROCESS: BiCMOS ADC Power-Supply Rejection ADC power-supply rejection (PSR) is defined as the shift in offset error when the power supply is moved from the minimum operating voltage to the maximum operating voltage. DAC Power-Supply Rejection DAC PSR is the amount of change in the converter’s value at full-scale as the power-supply voltage changes from its nominal value.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports AIN0 REF1 GPIOA0 GPIOA1 1 27 2 26 EOC DVDD 3 25 4 24 DGND DOUT 5 SCLK DIN OUT0 7 21 8 20 GPIOC1 GPIOC0 N.C. RES_SEL CS LDAC 9 19 OUT7 23 28 29 30 31 AIN7 N.C. AIN6 AIN5 AIN4 AIN3 33 32 AIN9 AIN8 34 REF2/AIN10 35 26 EOC DVDD 3 25 4 24 DGND DOUT 5 SCLK DIN OUT0 7 21 8 20 AIN1 N.C. AIN0 RES_SEL CS LDAC 9 19 OUT7 23 MAX1223 16 17 18 OUT5 OUT6 15 11 OUT2 OUT3 AVDD AGND N.C.
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports QFN THIN.EPS ______________________________________________________________________________________ 43 MAX1221/MAX1223/MAX1343 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.
MAX1221/MAX1223/MAX1343 12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports Revision History REVISION NUMBER REVISION DATE 1 12/07 DESCRIPTION Changed timing characteristic specification PAGES CHANGED 7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.