Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 28

General Description

The MAX1262/MAX1264 low-power, 12-bit analog-to-

digital converters (ADCs) feature a successive-approxi-

mation ADC, automatic power-down, fast wake-up

(2µs), an on-chip clock, +2.5V internal reference, and a

high-speed, byte-wide parallel interface. The devices

operate with a single +5V analog supply and feature a

LOGIC

pin that allows them to interface directly with a

+2.7V to +5.5V digital supply.

Power consumption is only 10mW (V

= V

LOGIC

) at a

400ksps max sampling rate. Two software-selectable

power-down modes enable the MAX1262/MAX1264 to

be shut down between conversions; accessing the par-

allel interface returns them to normal operation.

Powering down between conversions can cut supply

current to under 10µA at reduced sampling rates.

Both devices offer software-configurable analog inputs

for unipolar/bipolar and single-ended/pseudo-differen-

tial operation. In single-ended mode, the MAX1262 has

eight input channels and the MAX1264 has four input

channels (four and two input channels, respectively,

when in pseudo-differential mode).

Excellent dynamic performance and low power, com-

bined with ease of use and small package size, make

these converters ideal for battery-powered and data-

acquisition applications or for other circuits with demand-

ing power consumption and space requirements.

The MAX1262 is available in a 28-pin QSOP package,

while the MAX1264 comes in a 24-pin QSOP. For pin-

compatible +3V, 12-bit versions, refer to the MAX1261/

MAX1263 data sheet.

Applications

Industrial Control Systems Data Logging

Energy Management Patient Monitoring

Data-Acquisition Systems Touch Screens

Features

♦ 12-Bit Resolution, ±0.5 LSB Linearity

♦ +5V Single-Supply Operation

♦ User-Adjustable Logic Level (+2.7V to +5.5V)

♦ Internal +2.5V Reference

♦ Software-Configurable Analog Input Multiplexer

8-Channel Single Ended/

4-Channel Pseudo-Differential (MAX1262)

4-Channel Single Ended/

2-Channel Pseudo-Differential (MAX1264)

♦ Software-Configurable Unipolar/Bipolar Analog

Inputs

♦ Low Current

2.5mA (400ksps)

1.0mA (100ksps)

400µA (10ksps)

2µA (Shutdown)

♦ Internal 6MHz Full-Power Bandwidth Track/Hold

♦ Byte-Wide Parallel (8 + 4) Interface

♦ Small Footprint

28-Pin QSOP (MAX1262)

24-Pin QSOP (MAX1264)

MAX1262/MAX1264

400ksps, +5V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________ Maxim Integrated Products 1

19-2720; Rev 0; 04/03

Ordering Information

Pin Configurations

Ordering Information continued at end of data sheet.

Typical Operating Circuits appear at end of data sheet.

LOGIC

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CLKWR

INT

D0/D8

D1/D9

D2/D10

D3/D11

HBEN

QSOP

MAX1264

TOP VIEW

Pin Configurations continued at end of data sheet.

EVALUATION KIT

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

INL

(LSB)

MAX1262ACEI 0°C to +70°C

28 QSOP

±0.5

MAX1262BCEI 0°C to +70°C

28 QSOP

±1

MAX1262AEEI -40°C to +85°C

28 QSOP

±0.5

MAX1262BEEI -40°C to +85°C

28 QSOP

±1

Summary of content (20 pages)

PAGE 1
9-2720; Rev 0; 04/03 KIT ATION EVALU E L B AVAILA 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface The MAX1262 is available in a 28-pin QSOP package, while the MAX1264 comes in a 24-pin QSOP. For pincompatible +3V, 12-bit versions, refer to the MAX1261/ MAX1263 data sheet.
PAGE 2
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V VLOGIC to GND.........................................................-0.3V to +6V CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.
PAGE 3
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Analog Supply Voltage VDD 4.5 5.5 V Digital Supply Voltage VLOGIC 2.7 VDD + 0.
PAGE 5
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = VLOGIC = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.2 -0.3 -0.3 -0.4 -0.4 2000 3000 4000 1 0 5000 1000 2000 3000 4000 5000 0.1 1 10 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE RL = ∞ CODE = 101010100000 10k 100k 1000k 990 980 STANDBY IDD (µA) 2.
PAGE 7
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE OFFSET ERROR (LSB) 2.51 2.50 2.50 2.49 2.49 0 -1.0 2.48 5.00 5.25 5.50 -40 -15 VDD (V) 10 35 60 4.50 85 -1 1.5 0 -2 10 35 60 0 4.50 85 4.75 5.00 5.25 VDD (V) LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE LOGIC SUPPLY CURRENT vs.
PAGE 8
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.
PAGE 9
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface REFADJ AV = 2.05 (CH7) 17kΩ (CH6) (CH5) (CH4) CH3 CH2 ANALOG INPUT MULTIPLEXER MAX1262/MAX1264 REF 1.22V REFERENCE T/H CHARGE REDISTRIBUTION 12-BIT DAC COMP CH1 CH0 12 COM SUCCESSIVEAPPROXIMATION REGISTER CLK CLOCK 4 CS WR CONTROL LOGIC & LATCHES RD INT 8 4 8 MUX 8 8 TRI-STATE, BIDIRECTIONAL I/O INTERFACE MAX1262 MAX1264 HBEN VDD VLOGIC GND D0–D7 8-BIT DATA BUS ( ) ARE FOR MAX1262 ONLY. Figure 2.
PAGE 10
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 12-BIT CAPACITIVE DAC 12-BIT CAPACITIVE DAC REF REF CH0 CH1 CH2 12pF CH3 CH4 CSWITCH CH5 CH6 CH7 COM COMPARATOR INPUT CHOLD MUX – + ZERO CH0 ZERO 12pF TRACK T/H SWITCH RIN 800Ω CH1 RIN 800Ω CSWITCH CH2 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
PAGE 11
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval (three external clock cycles or approximately 1µs in internal clock mode) ends (Figure 4).
PAGE 12
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tACQ tCSWS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D7–D0 ACQMOD = 0 tINT1 INT RD HBEN tD0 tTR tD01 HIGH-Z HIGH/LOW BYTE VALID DOUT HIGH/LOW BYTE VALID HIGH-Z Figure 4.
PAGE 13
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ACQUISITION STARTS tCP External Clock Mode To select the external clock mode, bits D6 and D7 of the control byte must be set to 1. Figure 6a shows the clock and WR timing relationship for internal and external (Figure 6b) acquisition modes with an external clock. Proper operation requires a 100kHz to 7.6MHz clock frequency with 30% to 70% duty cycle.
PAGE 14
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Input Format The control byte is latched into the device on pins D7– D0 during a write command. Table 2 shows the control byte format. Digital Interface Input (control byte) and output data are multiplexed on a tri-state parallel interface. This parallel interface (I/O) can easily be interfaced with standard µPs. Signals CS, WR, and RD control the write and read operations.
PAGE 15
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.
PAGE 16
MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface only 50µs is required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode. Note: Bypass capacitors larger than 4.7µF between REF and GND result in longer power-up delays. Transfer Function Table 6 shows the full-scale voltage ranges for unipolar and bipolar modes.
PAGE 17
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface __________________________Definitions MAX1262/MAX1264s’ INL is measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
PAGE 18
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1262/MAX1264 the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. SUPPLIES 3V/5V R* = 5Ω Signal-to-Noise Plus Distortion VLOGIC = 3V/5V GND SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS) 4.7µF Effective Number of Bits 0.
PAGE 19
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface CLK +2.7V TO +5.5V VLOGIC +5V MAX1262 VDD µP CONTROL INPUTS CS REF WR REFADJ 4.7µF +2.7V TO +5.5V VLOGIC +5V MAX1264 VDD +2.5V 0.1µF RD CLK µP CONTROL INPUTS CS REF WR REFADJ +2.5V HBEN 4.7µF 0.
PAGE 20
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) QSOP.EPS MAX1262/MAX1264 400ksps, +5V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.