Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 28

General Description

The MAX1265/MAX1267 low-power, 12-bit analog-to-

digital converters (ADCs) feature a successive-approxi-

mation ADC, automatic power-down, fast wake-up

(2µs), an on-chip clock, +2.5V internal reference, and a

high-speed 12-bit parallel interface. They operate with

a single +2.7V to +3.6V analog supply.

Power consumption is only 5.4mW at the maximum

sampling rate of 265ksps. Two software-selectable

power-down modes enable the MAX1265/MAX1267 to

be shut down between conversions; accessing the par-

allel interface returns them to normal operation.

Powering down between conversions can reduce sup-

ply current below 10µA at lower sampling rates.

Both devices offer software-configurable analog inputs

for unipolar/bipolar and single-ended/pseudo-differen-

tial operation. In single-ended mode, the MAX1265 has

six input channels and the MAX1267 has two (three

input channels and one input channel, respectively,

when in pseudo-differential mode).

Excellent dynamic performance and low power, com-

bined with ease of use and small package size, make

these converters ideal for battery-powered and data-

acquisition applications or for other circuits with demand-

ing power-consumption and space requirements. The

MAX1265 is offered in a 28-pin QSOP package, while the

MAX1267 comes in a 24-pin QSOP. For pin-compatible

+5V, 12-bit versions, refer to the MAX1266/MAX1268

data sheet.

Applications

Industrial Control Systems Data Logging

Energy Management Patient Monitoring

Data-Acquisition Systems Touch Screens

Features

♦ 12-Bit Resolution, ±0.5 LSB Linearity

♦ +3V Single-Supply Operation

♦ Internal +2.5V Reference

♦ Software-Configurable Analog Input Multiplexer

6-Channel Single Ended/

3-Channel Pseudo Differential (MAX1265)

2-Channel Single Ended/

1-Channel Pseudo Differential (MAX1267)

♦ Software-Configurable Unipolar/Bipolar

Analog Inputs

♦ Low Current

1.9mA (265ksps)

1.0mA (100ksps)

400µA (10ksps)

2µA (Shutdown)

♦ Internal 3MHz Full-Power Bandwidth Track/Hold

♦ Parallel 12-Bit Interface

♦ Small Footprint

28-Pin QSOP (MAX1265)

24-Pin QSOP (MAX1267)

MAX1265/MAX1267

265ksps, +3V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________ Maxim Integrated Products 1

19-2721; Rev 0; 04/03

28 QSOP ±10°C to +70°CMAX1265BCEI

INL

(LSB)

±0.528 QSOP

PIN-PACKAGETEMP RANGE

0°C to +70°C

MAX1265ACEI

PART

Ordering Information

Pin Configurations

Typical Operating Circuits appear at end of data sheet.

D10

D11

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CH4

CH5

CLK

INT

QSOP

TOP VIEW

MAX1265

Pin Configurations continued at end of data sheet.

28 QSOP ±0.5-40°C to +85°CMAX1265AEEI

28 QSOP ±1-40°C to +85°CMAX1265BEEI

24 QSOP ±0.5-40°C to +85°CMAX1267AEEG

24 QSOP ±1-40°C to +85°CMAX1267BEEG

24 QSOP ±10°C to +70°CMAX1267BCEG

±0.524 QSOP0°C to +70°C

MAX1267ACEG

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Summary of content (19 pages)

PAGE 1
9-2721; Rev 0; 04/03 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Power consumption is only 5.4mW at the maximum sampling rate of 265ksps. Two software-selectable power-down modes enable the MAX1265/MAX1267 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can reduce supply current below 10µA at lower sampling rates.
PAGE 2
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CH0–CH5, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD + 0.
PAGE 3
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface TIMING CHARACTERISTICS (VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 3000 4000 10 WITH EXTERNAL REFERENCE 0 0 5000 1000 SUPPLY CURRENT vs. SUPPLY VOLTAGE 5000 0.1 IDD (mA) 1.95 RL = ∞ CODE = 101010100000 1.9 1.90 1.8 1.85 1.7 1.80 3.3 3.6 10k 100k 920 900 890 880 -40 -15 10 35 60 2.7 85 3.0 3.3 3.
PAGE 6
Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.51 2.50 2.50 2.49 2.49 -0.5 OFFSET ERROR (LSB) 2.51 OFFSET ERROR vs. SUPPLY VOLTAGE 0 MAX1265/67 toc10 2.52 VREF (mA) 2.52 3.0 2.7 3.3 -2.5 -40 3.6 -15 10 60 35 85 OFFSET ERROR vs. TEMPERATURE 3.3 -1.0 -1.5 MAX1265/67 toc13 0 -1.0 -2.0 60 85 -0.5 -1.0 -2.0 -3.0 35 0 -1.5 -2.0 -2.5 0.
PAGE 7
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.
PAGE 8
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1265/MAX1267 Pin Description (continued) PIN NAME FUNCTION 21 REF Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND when using the internal reference. 26 22 VDD Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND. 27 23 D11 Tri-State Digital Output (D11) 28 24 D10 Tri-State Digital Output (D10) MAX1265 MAX1267 25 REF REFADJ AV = 2.
PAGE 9
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the 12-BIT CAPACITIVE DAC 12-BIT CAPACITIVE DAC VREF CH0 VREF COMPARATOR INPUT CHOLD MUX – + ZERO CH0 12pF CH2 CSWITCH CH3 RIN 800Ω CH1 CSWITCH HOLD TRACK TRACK AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
PAGE 10
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1) A2 A1 A0 CH0 0 0 0 + 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 CH1 CH2* CH3* CH4* CH5* COM - + + + + + - *Channels CH2–CH5 apply to MAX1265 only. Table 3.
PAGE 11
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1265/MAX1267 tCS CS tACQ tCSWS tCSWH tWR tCONV WR tDH tDS CONTROL BYTE D11–D0 ACQMOD = 0 tINT1 INT RD tTR tD0 HIGH-Z VALID DATA DOUT HIGH-Z Figure 4. Conversion Timing Using Internal Acquisition Mode Together with the input impedance, this capacitor forms an RC filter, limiting the ADC’s signal bandwidth.
PAGE 12
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tCSWS tWR tACQ tCSWH tCONV WR tDH tDS CONTROL BYTE ACQMOD = 1 D11–D0 CONTROL BYTE ACQMOD = 0 tINT1 INT RD tD0 HIGH-Z tTR HIGH-Z VALID DATA DOUT Figure 5. Conversion Timing Using External Acquisition Mode External Acquisition Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisition and conversion times.
PAGE 13
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1265/MAX1267 ACQUISITION STARTS CONVERSION STARTS ACQUISITION ENDS tCP CLK tCWS tCH WR tCL WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = 0 tCWH ACQUISITION STARTS CONVERSION STARTS ACQUISITION ENDS CLK WR ACQMOD = 0 WR GOES HIGH WHEN CLK IS LOW. Figure 6a.
PAGE 14
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Table 4. Control-Byte Format D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD SGL/DIF UNI/BIP A2 A1 A0 An internal buffer is designed to provide +2.5V at REF for both the MAX1265 and MAX1267. The internally trimmed +1.22V reference is buffered with a +2.05V/V gain. VDD = +3V 50kΩ MAX1265 MAX1267 330kΩ 50kΩ REFADJ REF GND 0.01µF 4.7µF GND Figure 7.
PAGE 15
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1265/MAX1267 Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation UNIPOLAR MODE BIPOLAR MODE Zero scale COM Zero scale Full scale VREF + COM Positive full scale VREF/2 + COM Negative full scale -VREF/2 + COM OUTPUT CODE OUTPUT CODE 111 . . . 111 FS = REF + COM 111 . . . 110 ZS = COM 1 LSB = 100 . . . 010 FULL-SCALE TRANSITION REF 4096 FS = 011 . . . 110 ZS = COM 000 . . . 001 000 .
PAGE 16
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 1 CLK WR RD ; ; 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D11–D0 CONTROL WORD D7–D0 D11– D0 CONTROL WORD ACQUISITION STATE CONVERSION ACQUISITION SAMPLING INSTANT Figure 10. Timing Diagram for Fastest Conversion the data bus during acquisition or conversion can cause additional supply noise, which can make it difficult to achieve true 12-bit performance.
PAGE 17
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1265/MAX1267 is measured using the endpoint method.
PAGE 18
MAX1265/MAX1267 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Typical Operating Circuits CLK CLK +3V MAX1265 VDD µP CONTROL INPUTS CS REF WR REFADJ RD D11 INT 0.1µF µP 4.7µF CONTROL INPUTS CS REF WR REFADJ OUTPUT STATUS D11 D10 D9 D9 D8 D8 D7 D7 D5 D4 D3 D2 D1 D0 CH5 D5 CH3 D4 ANALOG INPUTS 4.7µF INT OUTPUT STATUS D3 CH1 D2 CH0 D1 COM D0 CH1 ANALOG INPUTS CH0 COM GND GND µP DATA BUS 0.1µF D6 CH4 CH2 +2.
PAGE 19
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.