Datasheet

MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
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Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a


t
SDV
t
SSTRB
SCLK 12
t
STR
SSTRB
SCLK
CS
t
SSTRB

HIGH-Z HIGH-Z
Figure 7. External Clock Mode—SSTRB Detailed Timing
CS
SCLK
DIN
DOUT
A/D STATE
13 19 24 26 31 32
14
16
37
START
SEL2 SEL1 SEL0 BIPRNG PD1 PD0
D11 D10 D9 D7D8 D6 D5 D4 D2D3 D1 D0
LSB
81
MSB
LSBMSB
START
SEL2 SEL1 SEL0 BIPRNG PD1 PD0
START
SEL2
CONTROL BYTE 0
RESULT
CONTROL BYTE 1 CONTROL BYTE 2
18 SCLK
18 SCLK
SSTRB
D10D11 D9 D8 D6D7 D5
RESULT 1
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
ACQUISITION
6 SCLK
CONVERSION
12 SCLK
HIGH-Z
HIGH-Z
Figure 8. External Clock Mode—18 Clocks/Conversion Timing