Datasheet
MAX1270/MAX1271
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
_______________________________________________________________________________________ 9
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
and enters hold/conversion mode when the timed
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
When operating in bipolar (MAX1270 and MAX1271) or
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
for unipolar mode, the channel input resistance (R
IN
)
becomes a fixed 5.12kΩ (typ). Source impedances
below 15kΩ (0 to V
REF
) and 5kΩ (0 to V
REF
/2) do not
significantly affect the AC performance of the ADC.
The acquisition time (t
ACQ
) is a function of the source
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
100kΩ
510kΩ
24kΩ
REFADJ
+5V
MAX1270
MAX1271
0.01µF
CH2
CH1
CH0
SHDN
CH3
CH4
CH5
CH6
CH7
REFADJ
REF
V
DD
AGND
DGND
MAX1270
MAX1271
12-BIT SAR ADC
IN
REF
CLOCK
OUT
T/H
2.5V
REFERENCE
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
Av =
1.638
INT
CLOCK
DIN
SSTRB DOUT CS SCLK
SERIAL INTERFACE LOGIC
10kΩ
+4.096V
0.5mA
DOUT
OR
SSTRB
+5V
a)
HIGH IMPEDANCE TO V
OH
, V
OL
TO
V
OH
AND V
OH
TO HIGH IMPEDANCE
HIGH IMPEDANCE TO V
OH
, V
OL
TO
V
OH
AND V
OH
TO HIGH IMPEDANCE
b)
C
LOAD
C
LOAD
5mA
DOUT
OR
SSTRB
Figure 1. Reference-Adjust Circuit
Figure 3. Block Diagram
Figure 2. Output Load Circuit for Timing Characteristics