Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 28

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General Description

The MAX1291/MAX1293 low-power, 12-bit analog-to-dig-

ital converters (ADCs) feature a successive-approxima-

tion ADC, automatic power-down, fast wake-up (2µs), an

on-chip clock, +2.5V internal reference, and a high-

speed, byte-wide parallel interface. They operate with a

single +3V analog supply and feature a V

LOGIC

pin that

allows them to interface directly with a +1.8V to +5.5V

digital supply.

Power consumption is only 5.7mW (V

= V

LOGIC

) at the

maximum sampling rate of 250ksps. Two software-selec-

table power-down modes enable the MAX1291/

MAX1293 to be shut down between conversions;

accessing the parallel interface returns them to normal

operation. Powering down between conversions can cut

supply current to under 10µA at reduced sampling rates.

Both devices offer software-configurable analog inputs

for unipolar/bipolar and single-ended/pseudo-differen-

tial operation. In single-ended mode, the MAX1291 has

eight input channels and the MAX1293 has four input

channels (four and two input channels, respectively,

when in pseudo-differential mode).

Excellent dynamic performance and low power, com-

bined with ease of use and small package size, make

these converters ideal for battery-powered and data-

acquisition applications or for other circuits with demand-

ing power consumption and space requirements.

The MAX1291/MAX1293 tri-states INT when CS goes

high. Refer to MAX1261/MAX1263 if tri-stating INT is not

desired.

The MAX1291 is available in a 28-pin QSOP package,

while the MAX1293 is available in a 24-pin QSOP. For

pin-compatible +5V, 12-bit versions, refer to the

MAX1290/MAX1292 data sheet.

Applications

Industrial Control Systems Data Logging

Energy Management Patient Monitoring

Data-Acquisition Systems Touch Screens

Features

♦ 12-Bit Resolution, ±0.5 LSB Linearity

♦ +3V Single Operation

♦ User-Adjustable Logic Level (+1.8V to +3.6V)

♦ Internal +2.5V Reference

♦ Software-Configurable, Analog Input Multiplexer

8-Channel Single-Ended/

4-Channel Pseudo-Differential (MAX1291)

4-Channel Single-Ended/

2-Channel Pseudo-Differential (MAX1293)

♦ Software-Configurable, Unipolar/Bipolar Inputs

♦ Low Power: 1.9mA (250ksps)

1.0mA (100ksps)

400µA (10ksps)

2µA (Shutdown)

♦ Internal 3MHz Full-Power Bandwidth Track/Hold

♦ Byte-Wide Parallel (8 + 4) Interface

♦ Small Footprint: 28-Pin QSOP (MAX1291)

24-Pin QSOP (MAX1293)

MAX1291/MAX1293

250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________ Maxim Integrated Products 1

19-1532; Rev 3; 12/02

PART

MAX1291ACEI

0°C to +70°C

TEMP RANGE

PIN-PACKAGE

28 QSOP

Ordering Information

Pin Configurations

±0.5

INL

(LSB)

MAX1291BCEI

0°C to +70°C

±128 QSOP

Ordering Information continued at end of data sheet.

Typical Operating Circuits appear at end of data sheet.

1514 CH7CS

QSOP

TOP VIEW

LOGIC

REF

REFADJ

GND

COM

CH0

CH1

CH2

CH3

CH4

CH5

CH6CLK

INT

D0/D8

D1/D9

D2/D10

D3/D11

HBEN

MAX1291

Pin Configurations continued at end of data sheet.

EVALUATION KIT

AVAILABLE

MAX1291BEEI

MAX1291AEEI

-40°C to +85°C

±1

-40°C to +85°C

±0.528 QSOP

28 QSOP

Summary of content (20 pages)

PAGE 1
9-1532; Rev 3; 12/02 KIT ATION EVALU E L B AVAILA 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Applications Features ♦ 12-Bit Resolution, ±0.5 LSB Linearity ♦ +3V Single Operation ♦ User-Adjustable Logic Level (+1.8V to +3.6V) ♦ Internal +2.
PAGE 2
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V VLOGIC to GND.........................................................-0.3V to +6V CH0–CH7, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND ................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.
PAGE 3
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.7 3.6 V 1.8 VDD + 0.
PAGE 5
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 -0.2 0 -0.1 -0.3 -0.3 -0.4 -0.4 WITH INTERNAL REFERENCE 100 WITH EXTERNAL REFERENCE 10 -0.5 2000 3000 4000 5000 0 1000 DIGITAL OUTPUT CODE 3000 4000 1 5000 0.1 100 RL = ∞ CODE = 101010100000 2.1 1.95 1.9 1.90 1.8 1.85 1.7 1.80 3.
PAGE 7
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.51 2.50 2.50 2.49 2.49 3.0 3.3 -2.5 -40 3.6 -15 10 35 60 85 2.7 -1.5 -1 -2 35 60 3.0 3.3 VDD (V) LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE LOGIC SUPPLY CURRENT vs.
PAGE 8
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.
PAGE 9
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Converter Operation The MAX1291/MAX1293 ADCs use a successiveapproximation (SAR) conversion technique and an input track/hold (T/H) stage to convert an analog input signal to a 12-bit digital output. Their parallel (8 + 4) output format provides an easy interface to standard microprocessors (µPs). Figure 2 shows the simplified internal architecture of the MAX1291/MAX1293.
PAGE 10
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Track/Hold 12-BIT CAPACITIVE DAC REF COMPARATOR INPUT CHOLD MUX – + CH0 CH1 ZERO 12pF RIN 800Ω CH2 CH3 CH4 CSWITCH HOLD TRACK CH5 CH6 CH7 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
PAGE 11
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval ends (three external cycles or approximately 1µs in internal clock mode) (Figure 4).
PAGE 12
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tCSWS tACQ tCONV tCSWH tWR WR tDH tDS CONTROL BYTE D7–D0 ACQMOD = "0" INT HIGH-Z HIGH-Z tINT1 RD HBEN tD0 HIGH-Z tTR tD01 HIGH/LOW BYTE VALID DOUT HIGH/LOW BYTE VALID HIGH-Z Figure 4.
PAGE 13
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Internal Clock Mode Select internal clock mode to release the µP from the burden of running the SAR conversion clock. To select this mode, bit D7 of the control byte must be set to 1 and bit D6 must be set to 0. The internal clock frequency is then selected, resulting in a conversion time of 3.6µs. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating.
PAGE 14
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWS tDH WR ACQMOD = "0" WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = "1" ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK tCWH tDH WR ACQMOD = "1" WR GOES HIGH WHEN CLK IS LOW. ACQMOD = "0" Figure 6b. External Clock and WR Timing (External Acquisition Mode) Table 2.
PAGE 15
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface A2 A1 A0 CH0 CH1 CH2 CH3 0 0 0 + - 0 0 1 - + 0 1 0 1 CH4* CH5* CH6* CH7* 0 + - 1 1 - + 0 0 + - 1 0 1 - + 1 1 0 + - 1 1 1 - + *Channels CH4–CH7 apply to MAX1291 only. Internal and External Reference Internal Reference With the internal reference, the full-scale range is +2.5V with unipolar inputs and ±1.25V with bipolar inputs.
PAGE 16
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to V DD . The DC input resistance at REF is 25kΩ. Therefore, an external reference at REF must deliver up to 200µA DC load current during a conversion and have an output impedance less than 10Ω. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7µF capacitor.
PAGE 17
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface UNIPOLAR MODE BIPOLAR MODE Full Scale VREF + COM Positive Full Scale Zero Scale COM Zero Scale COM — — Negative Full Scale -VREF/2 + COM sion cycles, and 2 read cycles. This assumes that the results of the last conversion are read before the next control byte is written.
PAGE 18
MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK WR RD HBEN D7–D0 CONTROL BYTE D7–D0 D11–D8 LOW BYTE STATE CONTROL BYTE HIGH BYTE D11–D8 LOW BYTE HIGH BYTE ACQUISITION CONVERSION ACQUISITION D7–D0 SAMPLING INSTANT Figure 10.
PAGE 19
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface CLK +1.8V TO +3.6V VLOGIC CS REF WR REFADJ 4.7µF +1.8V TO +3.6V +3V MAX1293 VDD +2.5V 0.1µF RD VLOGIC +3V MAX1291 VDD µP CONTROL INPUTS CLK µP CONTROL INPUTS CS REF WR REFADJ 4.7µF 0.1µF RD HBEN +2.
PAGE 20
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX1291/MAX1293 250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.