Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QSOP 28

General Description

The MAX1294/MAX1296 low-power, 12-bit analog-to-

digital converters (ADCs) feature a successive-approxi-

mation ADC, automatic power-down, fast wake-up

(2µs), an on-chip clock, +2.5V internal reference, and a

high-speed 12-bit parallel interface. They operate with

a single +5V analog supply.

Power consumption is only 10mW at the maximum sam-

pling rate of 420ksps. Two software-selectable power-

down modes enable the MAX1294/MAX1296 to be shut

down between conversions; accessing the parallel

interface returns them to normal operation. Powering

down between conversions can reduce supply below

10µA at lower sampling rates.

Both devices offer software-configurable analog inputs for

unipolar/bipolar and single-ended/pseudo-differential

operation. In single-ended mode, the MAX1294 has six

input channels and the MAX1296 has two (three input

channels and one input channel, respectively, when in

pseudo-differential mode).

Excellent dynamic performance and low power, com-

bined with ease of use and small package size, make

these converters ideal for battery-powered and data-

acquisition applications or for other circuits with demand-

ing power-consumption and space requirements.

The MAX1294/MAX1296 tri-states INT when CS goes

high. Refer to MAX1266/MAX1268 if tri-stating INT is not

desired.

The MAX1294 is offered in a 28-pin QSOP package, while

the MAX1296 is available in a 24-pin QSOP. For pin-com-

patible +3V, 12-bit versions, see the MAX1295/MAX1297.

Applications

Industrial Control Systems Data Logging

Energy Management Patient Monitoring

Data-Acquisition Systems Touchscreens

Features

♦ 12-Bit Resolution, ±0.5 LSB Linearity

♦ Single +5V Operation

♦ Internal +2.5V Reference

♦ Software-Configurable Analog Input Multiplexer

6-Channel Single-Ended/

3-Channel Pseudo-Differential (MAX1294)

2-Channel Single-Ended/

1-Channel Pseudo-Differential (MAX1296)

♦ Software-Configurable Unipolar/Bipolar

Analog Inputs

♦ Low Current

2.8mA (420ksps)

1.0mA (100ksps)

400µA (10ksps)

2µA (Shutdown)

♦ Internal 6MHz Full-Power Bandwidth Track/Hold

♦ Parallel 12-Bit Interface

♦ Small Footprint

28-Pin QSOP (MAX1294)

24-Pin QSOP (MAX1296)

MAX1294/MAX1296

420ksps, +5V, 6-/2-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

________________________________________________________________ Maxim Integrated Products 1

19-1533; Rev 2; 12/02

PART

MAX1294ACEI

MAX1294BCEI 0°C to +70°C

0°C to +70°C

TEMP RANGE PIN-PACKAGE

28 QSOP

Ordering Information

Pin Configurations

INL

(LSB)

±0.5

±1

Typical Operating Circuits appear at end of data sheet.

D10

D11

REF

REFADJ

GND

COM

CH0

CH1

CLK

WRRD

INT

QSOP

TOP VIEW

MAX1296

Pin Configurations continued at end of data sheet.

MAX1294AEEI -40°C to +85°C 28 QSOP ±0.5

MAX1294BEEI -40°C to +85°C 28 QSOP ±1

EVALUATION KIT

AVAILABLE

MAX1296ACEG

MAX1296BCEG

MAX1296AEEG -40°C to +85°C

0°C to +70°C

0°C to +70°C 24 QSOP

24 QSOP

24 QSOP ±0.5

MAX1296BEEG -40°C to +85°C 24 QSOP ±1

±0.5

±1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Summary of content (19 pages)

PAGE 1
9-1533; Rev 2; 12/02 KIT ATION EVALU E L B A AVAIL 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Power consumption is only 10mW at the maximum sampling rate of 420ksps. Two software-selectable powerdown modes enable the MAX1294/MAX1296 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can reduce supply below 10µA at lower sampling rates.
PAGE 2
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CH0–CH5, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD + 0.
PAGE 3
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface (VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface TIMING CHARACTERISTICS (VDD = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 0.4 0.3 0.2 0.1 0.1 DNL (LSB) 0.2 0 -0.1 0 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 4000 5000 WITH EXTERNAL REFERENCE 0 0 1000 DIGITAL OUTPUT CODE SUPPLY CURRENT vs. SUPPLY VOLTAGE 3000 4000 1 10 RL = ∞ CODE = 101010100000 2.2 IDD (mA) 1k 10k 100k 1M STANDBY CURRENT vs. SUPPLY VOLTAGE 2.1 2.0 100 fSAMPLE (Hz) 990 980 STANDBY IDD (µA) RL = ∞ CODE = 101010100000 2.1 IDD (mA) 0.
PAGE 6
Typical Operating Characteristics (continued) (VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) REFERENCE VOLTAGE vs. TEMPERATURE MAX1294/6toc10 2.51 2.50 2.50 2.49 2.49 1.0 OFFSET ERROR (LSB) 2.51 2.52 VREF (V) 4.50 4.75 5.00 5.25 -1.0 -40 5.50 -15 10 35 60 85 5.00 GAIN ERROR (LSB) 0 35 60 0 4.50 85 1.0 0.5 -2 -2 4.75 5.00 5.25 5.
PAGE 7
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.
PAGE 8
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1294/MAX1296 Pin Description (continued) PIN NAME FUNCTION 21 REF Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND when using the internal reference. 26 22 VDD Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND. 27 23 D11 Three-State Digital Output (D11) 28 24 D10 Three-State Digital Output (D10) MAX1294 MAX1296 25 REF REFADJ AV = 2.
PAGE 9
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tial mode, IN+ and IN- are selected from analog input pairs (Table 3) and are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5 LSB (±0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.
PAGE 10
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1) A2 A1 A0 CH0 0 0 0 + 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 CH1 CH2* CH3* CH4* CH5* COM - + + + + + - *Channels CH2–CH5 apply to MAX1294 only. Table 3.
PAGE 11
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tACQ = 9 (RS + RIN) CIN where RS is the source impedance of the input signal, RIN (800Ω) is the input resistance, and CIN (12pF) is the ADC’s input capacitance. Source impedances below 3kΩ have no significant impact on the MAX1294/ MAX1296’s AC performance. Higher source impedances can be used if a 0.01µF capacitor is connected to the individual analog inputs.
PAGE 12
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface tCS CS tCSWS tACQ tCONV tCSWH tWR WR tDH tDS CONTROL BYTE D7–D0 ACQMOD = "0" INT HIGH-Z HIGH-Z tINT1 RD tD0 DOUT tTR HIGH-Z VALID DATA HIGH-Z Figure 4. Conversion Timing Using Internal Acquisition Mode tCS CS tCSWS tWR tACQ tCSHW tCONV WR tDH tDS CONTROL BYTE ACQMOD = "1" D7–D0 tOH CONTROL BYTE ACQMOD = "0" HIGH-Z HIGH-Z INT tINT1 RD tD0 HIGH-Z tTR VALID DATA DOUT Figure 5.
PAGE 13
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ACQUISITION STARTS tCP Digital Interface The input and output data are multiplexed on a threestate parallel interface (I/O) that can easily be interfaced with standard µPs. The signals CS, WR, and RD control the write and read operations. CS represents the chip-select signal, which enables a µP to address the MAX1294/MAX1296 as an I/O port.
PAGE 14
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Table 4. Control-Byte Format D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD SGL/DIF UNI/BIP A2 A1 A0 Input Format The control bit sequence is latched into the device on pins D7–D0 during a write command. Table 4 shows the control-byte format. Output Data Format The 12-bit-wide output format for both the MAX1294/ MAX1296 is binary in unipolar mode and two’s complement in bipolar mode.
PAGE 15
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1294/MAX1296 Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation UNIPOLAR MODE BIPOLAR MODE Full Scale VREF + COM Zero Scale COM Zero Scale COM — — Negative Full Scale -VREF/2 + COM 111 . . . 111 FS = REF + COM 111 . . . 110 ZS = COM FULL-SCALE TRANSITION 011 . . . 111 FS = REF + COM 2 011 . . . 110 ZS = COM 000 . . . 010 100 . . . 010 1 LSB = 100 . . . 000 REF 4096 000 . . .
PAGE 16
MAX1294/MAX1296 420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 1 CLK WR RD D7–D0 STATE CONTROL WORD ; ; 2 3 4 5 6 7 8 9 D11– D0 10 11 12 13 14 15 16 D11–D0 CONTROL WORD ACQUISITION CONVERSION ACQUISITION SAMPLING INSTANT Figure 10. Timing Diagram for Fastest Conversion tion or conversion can cause additional supplynoise, which can make it difficult to achieve true 12-bit performance.
PAGE 17
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1294/MAX1296 is measured using the endpoint method.
PAGE 18
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1294/MAX1296 Typical Operating Circuits CLK CLK +5V MAX1294 VDD µP CONTROL INPUTS CS REF WR REFADJ 0.1µF 4.
PAGE 19
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface QSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.