Datasheet

MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
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PIN
TSSOP UCSP
NAME FUNCTION
1B1 IV
L
1 Open-Drain-Compatible Input 1, Referenced to V
L
2B2 IV
L
2 Open-Drain-Compatible Input 2, Referenced to V
L
3A1 IV
L
3 Open-Drain-Compatible Input 3, Referenced to V
L
4A2 V
L
Logic Input Voltage, +0.9V ≤ V
L
≤ V
CC
. Bypass V
L
to GND with a 0.1µF
capacitor.
5A3 EN
Enable Input. When EN is pulled low, OV
CC
1 to OV
CC
6 and IV
L
1 to IV
L
6 are
tri-stated. Drive EN high (V
L
) for normal operation.
6A4 IV
L
4 Open-Drain-Compatible Input 4, Referenced to V
L
7B3 IV
L
5 Open-Drain-Compatible Input 5, Referenced to V
L
8B4 IV
L
6 Open-Drain-Compatible Input 6, Referenced to V
L
9C4OV
CC
6 CMOS Output 6, Referenced to V
CC
10 C3 OV
CC
5 CMOS Output 5, Referenced to V
CC
11 D4 OV
CC
4 CMOS Output 4, Referenced to V
CC
12 D3 GND Ground
13 D2 V
CC
V
CC
Input Voltage, +1.5V ≤ V
CC
≤ 3.6V. Bypass V
CC
to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on V
CC
.
14 D1 OV
CC
3 CMOS Output 3, Referenced to V
CC
15 C2 OV
CC
2 CMOS Output 2, Referenced to V
CC
16 C1 OV
CC
1 CMOS Output 1, Referenced to V
CC
MAX13002E/MAX13005E
Pin Descriptions (continued)