EVALUATION KIT AVAILABLE MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs General Description The MAX1300/MAX1301 multirange, low-power, 16-bit, successive-approximation, analog-to-digital converters (ADCs) operate from a single +5V supply and achieve throughput rates up to 115ksps. A separate digital supply allows digital interfacing with 2.7V to 5.25V systems using the SPI-/QSPI™-/MICROWIRE®-compatible serial interface.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Absolute Maximum Ratings AVDD1 to AGND1....................................................-0.3V to +6V AVDD2 to AGND2....................................................-0.3V to +6V DVDD to DGND........................................................-0.3V to +6V DVDDO to DGNDO..................................................-0.3V to +6V DVDD to DVDDO.....................................................-0.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Electrical Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Electrical Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Electrical Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Electrical Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range (±3 x VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Typical Operating Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) DIGITAL I/O SUPPLY CURRENT vs. DIGITAL I/O SUPPLY VOLTAGE TA = +85°C 4.95 5.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Typical Operating Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) CONTINUOUS EXTERNAL CLOCK MODE 2.38 13.95 MAX1300 toc08 2.39 13.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Typical Operating Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) 79 0.04 ±3 x VREF BIPOLAR RANGE 0.02 0 -0.02 -0.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Typical Operating Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Typical Operating Characteristics (continued) (VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input range, CDOUT = 50pF, CSSTRB = 50pF; unless otherwise noted.) FULL-POWER BANDWIDTH REFERENCE VOLTAGE vs.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Pin Description PIN NAME MAX1300 MAX1301 FUNCTION Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to AGND1 with a 0.1µF capacitor.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Pin Description (continued) PIN MAX1300 MAX1301 NAME FUNCTION 21 18 AGND3 Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together. 22 19 AVDD2 Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to AGND2 with a 0.1µF capacitor. 23 20 AGND2 Analog Ground 2.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Power Supplies To maintain a low-noise environment, the MAX1300 and MAX1301 provide separate power supplies for each section of circuitry. Table 1 shows the four separate power supplies. Achieve optimal performance using separate AVDD1, AVDD2, DVDD, and DVDDO supplies. Alternatively, connect AVDD1, AVDD2, and DVDD together as close to the device as possible for a convenient power connection.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs CS 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BYTE 2 BYTE 1 21 22 23 24 25 26 27 28 BYTE 3 29 30 31 32 BYTE 4 SSTRB S DIN C2 C1 C0 0 0 0 0 fSAMPLE fSCLK / 32 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* DOUT HOLD TRACK HIGH IMPEDANCE HOLD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 HIGH IMPEDANCE *TRACK AND HOLD TIMING IS CONT
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs CS SSTRB 1 SCLK 2 3 4 5 8 7 6 9 10 11 BYTE 1 DIN S C2 C1 C0 0 0 12 13 14 15 16 17 18 19 20 BYTE 2 0 21 22 23 24 25 26 27 28 BYTE 3 29 30 31 32 BYTE 4 0 HIGH IMPEDANCE DOUT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 fSAMPLE fSCLK / 32 + fINTCLK / 17 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* HOLD TRACK HOLD 100ns to 400ns 1 INTCLK** 2
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs CS SSTRB 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 BYTE 1 S DIN C2 C1 C0 0 0 13 14 15 16 17 18 19 20 BYTE 2 0 21 22 23 24 BYTE 3 0 HIGH IMPEDANCE DOUT B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 fSAMPLE fSCLK / 24 + fINTCLK / 28 SAMPLING INSTANT tACQ ANALOG INPUT TRACK AND HOLD* TRACK HOLD HOLD 100ns to 400ns 1 INTCLK** 2 3 10 11 12 13 14 25 26 27 28
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Table 3. Input Data Word Formats DATA BIT OPERATION D7 (START) D6 D5 D4 D3 D2 D1 D0 Conversion-Start Byte (Tables 4 and 5) 1 C2 C1 C0 0 0 0 0 Analog-Input Configuration Byte (Table 2) 1 C2 C1 C0 DIF/SGL R2 R1 R0 Mode-Control Byte (Table 7) 1 M2 M1 M0 1 0 0 0 CH6 CH7 Table 4.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs +6 x VREF FSR = 12 x VREF FSR = 6 x VREF FSR = 3 x VREF (CH_+) - (CH_-) (V) FSR = 6 x VREF 0 INPUT RANGE SELECTION BITS, R[2:0] EACH INPUT IS FAULT TOLERANT TO 16.5V. VREF = 4.096V. Figure 8.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Table 6.
8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs 12 12 8 8 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) MAX1300/MAX1301 4 0 -4 -8 -12 -16 -18 -12 -6 0 6 12 4 0 -4 -8 -12 -16 18 -18 -12 INPUT VOLTAGE (V) Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 3 x VREF) 0 6 12 18 Figure 10. Common-Mode Voltage vs.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs FSR FSR FFFF FFFF FFFE FFFE 8001 8000 7FFF 8001 FSR BINARY OUTPUT CODE (LSB [hex]) FFFD FSR BINARY OUTPUT CODE (LSB [hex]) FFFD 8000 7FFF 0003 0002 1 LSB = FSR x VREF 65,536 x 4.096V 0001 0003 1 LSB = FSR x VREF 65,536 x 4.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs tCSPW tCSS CS tCL SCLK tCH tCSH 1 8 tCP tDS DIN START SEL2 SEL1 SEL0 1 8 tDH DIF/SGL R2 R1 START R0 M2 ANALOG INPUT CONFIGURATION BYTE tDV M1 M0 1 0 0 0 MODE CONTROL BYTE tTR HIGH IMPEDANCE HIGH IMPEDANCE HIGH DOUT IMPEDANCE Figure 15.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Table 8. Mode-Control Bits M[2:0] M2 M1 M0 0 0 0 External Clock (DEFAULT) MODE 0 0 1 External Acquisition 0 1 0 Internal Clock 0 1 1 Reserved 1 0 0 Reset 1 0 1 Reserved 1 1 0 Partial Power-Down 1 1 1 Full Power-Down External Acquisition Mode (Mode 1) Reset (Mode 4) The slowest maximum throughput rate is achieved with the external acquisition method.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs • External-Acquisition-Mode Control Byte External Reference • Internal-Clock-Mode Control Byte • Reset Byte • Partial Power-Down-Mode Control Byte For external reference operation, disable the internal reference and reference buffer by connecting REFCAP to AVDD1. With AVDD1 connected to REFCAP, REF becomes a high-impedance input and accepts an external reference voltage.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs V+ IN 4.096V SAR ADC REF OUT 1.0µF 1x MAX1300 MAX1301 REF AVDD1 REFCAP 1.0µF MAX6341 GND 5kΩ 4.096V BANDGAP REFERENCE VRCTH AGND1 Figure 18. External Reference Operation Bridge Application Layout, Grounding, and Bypassing Dynamically Adjusting the Input Range Figure 1 shows the recommended system ground connections. Establish an analog ground point at AGND1 and a digital ground point at DGND.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs 4–20mA INPUT CH0 µC 250Ω MAX1300 4–20mA INPUT CH8 250Ω Figure 19. 4–20mA Application LOW-OFFSET DIFFERENTIAL AMPLIFIER CH0 µP CH1 MAX1300 MAX1301 REF BRIDGE Figure 20. Bridge Application Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Unipolar Offset Error -FSR to 0V When a zero-scale analog input voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE occurs at AGND1 - 0.5 LSB. Unipolar offset error is the amount of deviation between the measured zero-scale transition point and the ideal zero-scale transition point, with all untested channels grounded.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: SINAD − 1.76 ENOB = 6.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Block Diagram CONTROL LOGIC AND REGISTERS DVDDO CS DIN SSTRB DOUT SCLK DGNDO SERIAL I/O AVDD2 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND1 CLOCK ANALOG INPUT MUX AND MULTIRANGE CIRCUITRY PGA IN SAR ADC DVDD FIFO OUT DGND AVDD1 AGND3 REF AGND2 4.
MAX1300/MAX1301 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 16-Bit ADCs Revision History REVISION NUMBER REVISION DATE 0 11/06 Initial release 2 6/10 Updated Electrical Characteristics tables, TOCs to optimize yield. 3 12/11 Released MAX1300 and updated the Electrical Characteristics table.