Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal uMAX 10

General Description

The MAX1363/MAX1364 low-power, 12-bit, 4-channel

analog-to-digital converters (ADCs) feature a digitally

programmable window comparator with an interrupt out-

put for automatic system-monitoring applications. Once

configured, monitor mode automatically asserts an inter-

rupt when any analog input exceeds the programmed

upper or lower thresholds, without interaction to the

host. The MAX1363/MAX1364 respond to the SMBus™

alert, allowing quick identification of the alarming device

on a shared interrupt. A programmable delay between

monitoring intervals lowers power consumption for

reduced monitoring rates.

In addition, the MAX1363/MAX1364 integrate an inter-

nal voltage reference, a clock, and a 1.7MHz, high-

speed, I

C-compatible, 2-wire serial interface. The opti-

mized interface allows a maximum conversion rate of

94.4ksps in normal mode while reading back the con-

version results. Each of the four analog inputs is config-

urable for single-ended or fully differential operation

and unipolar or bipolar operation. Two scan modes uti-

lize on-chip random access memory (RAM) to allow

eight conversions of a selected channel or scanning of

a group of channels to reduce interface overhead.

These devices operate from a single 2.7V to 3.6V

(MAX1363) or 4.5V to 5.5V (MAX1364) supply and

require only 436µA at the maximum sampling rate of

133ksps in monitor mode and 670µA at the maximum

sampling rate of 94.4ksps. AutoShutdown™ powers

down the devices between conversions, reducing sup-

ply current to less than 1µA when idle.

The full-scale analog-input range is determined by the

internal reference or by an externally applied reference

voltage ranging from 1V to V

. The MAX1363 features

a 2.048V internal reference, and the MAX1364 features

a 4.096V internal reference.

The MAX1363/MAX1364 are available in a 10-pin

µMAX

package and are specified over the extended

(-40°C to +85°C) temperature range. For 10-bit applica-

tions, refer to the pin-compatible MAX1361/MAX1362

data sheet.

Applications

System Monitoring/Supervision

Servers/Workstations

High-Reliability Power Supplies

Medical Instrumentation

Features

♦ Monitor Mode

Programmable Lower/Upper Trip Threshold

Alarm-Status Register Records Fault Events

SMBus Alert Response

Programmable Sampling Intervals

♦ 12-Bit, I

C-Compatible ADC

±1 LSB INL, ±1 LSB DNL

♦ 4-Channel Single-Ended or 2-Channel Fully

Differential Inputs

♦ Software-Programmable Bipolar/Unipolar

Conversions

♦ Fast Sampling Rate

94.4ksps While Continuously Reading

Conversions

133ksps in Monitor Mode

♦ High-Speed, I

C-Compatible Serial Interface

100kHz/400kHz Standard/Fast Mode

Up to 1.7MHz High-Speed Mode

Six Available I

C Slave Addresses

♦ Single Supply

2.7V to 3.6V (MAX1363)

4.5V to 5.5V (MAX1364)

♦ Internal Reference

2.048V (MAX1363)

4.096V (MAX1364)

♦ External Reference: 1V to V

♦ Low Power

436µA in Monitor Mode (133ksps)

670µA at 94.4ksps

6µA at 1ksps

0.5µA in Power-Down Mode

♦ Small Package

10-Pin µMAX

MAX1363/MAX1364

4-Channel, 12-Bit System Monitors with Programmable

Trip Window and SMBus Alert Response

________________________________________________________________

Maxim Integrated Products

Ordering Information/Selector Guide

19-3338; Rev 3; 3/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE I

C SLAVE ADDRESS SUPPLY VOLTAGE (V)

MAX1363EUB+ -40°C to +85°C 10 µMAX 0110100/0110101 2.7 to 3.6

MAX1363MEUB+ -40°C to +85°C 10 µMAX 0110110/0110111 2.7 to 3.6

SMBus is a trademark of Intel Corporation.

AutoShutdown is a trademark of Maxim Integrated Products, Inc.

µMAX is a registered trademark of Maxim Integrated Products, Inc.

Typical Operating Circuit and Pin Configuration appear at

end of data sheet.

Ordering Information/Selector Guide continued at end of data sheet.

+Denotes a lead-free package.

Summary of content (25 pages)

PAGE 1
9-3338; Rev 3; 3/08 KIT ATION EVALU E L B AVAILA 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Features ♦ Monitor Mode Programmable Lower/Upper Trip Threshold Alarm-Status Register Records Fault Events SMBus Alert Response Programmable Sampling Intervals ♦ 12-Bit, I2C-Compatible ADC ±1 LSB INL, ±1 LSB DNL ♦ 4-Channel Single-Ended or 2-Channel Fully Differential Inputs ♦ Software-Programmable Bipolar/Unipolar Conversions ♦ Fast Sampling Rate 94.
PAGE 2
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V AIN0–AIN3, A0, REF to GND......................-0.3V to (VDD + 0.3V) SDA, SCL, INT to GND .............................................-0.3V to +6V Maximum Current Into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.
PAGE 3
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response (VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Track/Hold Acquisition Time MIN Internal Clock Frequency Aperture Delay (Note 6) TYP MAX 800 ns 2.
PAGE 4
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN fSAMPLE = Internal reference 133ksps, monitor mode External reference (Note 10) fSAMPLE = Internal reference 94.
PAGE 5
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response (VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Hold Time for START (S) Condition Low Period of the SCL Clock SYMBOL CONDITIONS MIN TYP MAX UNITS tHD, STA 0.6 µs tLOW 1.3 µs tHIGH 0.
PAGE 6
ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX1363), VDD = 4.5V to 5.5V (MAX1364), VREF = 2.048V (MAX1363), VREF = 4.096V (MAX1364), CREF = 0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Note 1: Devices configured for unipolar single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have been calibrated. Note 3: Offset nulled.
PAGE 7
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response 600 550 EXTERNAL REFERENCE 500 0.45 0.40 0.4 0.3 MAX1364 0.2 450 400 EXTERNAL REFERENCE MAX1363 0.30 0.25 0.20 MAX1363 0.15 0.05 300 0 -40 -25 -10 5 20 35 50 65 80 0 3.2 2.7 3.7 4.2 4.7 -40 -25 -10 5.2 5 20 35 50 65 80 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK) INTERNAL REFERENCE VOLTAGE vs.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.3V (MAX1363), VDD = 5V (MAX1364), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.) MONITOR-MODE SUPPLY CURRENT vs. SPEED GAIN ERROR vs. SUPPLY VOLTAGE 0.8 0.7 0.6 0.5 0.4 0.3 700 MAX1363/64 toc14 0.9 600 SUPPLY CURRENT (μA) MAX1363/64 toc13 1.
PAGE 9
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response MAX1363/MAX1364 tR tF SDA tSU.DAT tHD.DAT tLOW tHD.STA tBUF tSU.STA tSU.STO 9 SCL tSU.STA tHIGH tR tF S ACK Sr P S Figure 1a. F/S-Mode 2-Wire Serial-Interface Timing tRDA tFDA SDA tSU.DAT tHD.DAT tLOW tHD.STA tSU.STA 1 9 tSU.STO SCL tHD.STA tHIGH tRCL tFCL tRCL1 Sr ACK Sr P HS-MODE S F/S-MODE Figure 1b.
PAGE 10
Power Supply 12 conversion clock cycles and is equivalent to transferring a charge of 11pF x (VIN+ - VIN-) from CT/H to the binary-weighted capacitive DAC, forming a digital representation of the analog-input signal. Use a low source impedance to ensure an accurate sample. A source impedance of up to 1.5kΩ does not significantly degrade sampling accuracy. For larger source impedances, connect a 100pF capacitor from the analog input to GND or buffer the input.
PAGE 11
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Analog-Input Bandwidth The MAX1363/MAX1364 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals from aliasing into the frequency band of interest, use anti-aliasing filtering.
PAGE 12
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response External Clock See the Configuration/Setup Bytes (Write Cycle) section. When configured for external clock mode (CLK = 1), the MAX1363/MAX1364 use SCL as the conversion clock. In external clock mode, the MAX1363/MAX1364 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two SCL clock cycles later, the analog signal is acquired and the conversion begins.
PAGE 13
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response S 0 1 1 0 1 0 0 R/W ACK SDA 1 SCL 2 3 4 5 6 7 8 9 Figure 6. MAX1363/MAX1364 Slave Address Byte HS I2C Mode At power-up, the MAX1363/MAX1364 bus timing is set for fast mode (F/S mode, up to 400kHz I2C clock), which limits the conversion rate to approximately 22ksps. Switch to high-speed mode (HS mode, up to 1.7MHz I2C clock) to achieve conversion rates up to 94.4ksps.
PAGE 14
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response START CONDITION START R/W BIT FROM THE MASTER ADDRESS FROM THE MASTER 0 CONFIGURATION BYTE FROM THE MASTER A SETUP BYTE FROM THE MASTER A A STOP Figure 8.
PAGE 15
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by 7 address bits and a write bit (R/W = 0). If the address byte is successfully received, the MAX1363/MAX1364 (slave) issue an ACK. The master then writes to the slave. If the most significant bit (MSB) is 1, the slave recognizes the received byte as the setup byte (Table 4).
PAGE 16
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Table 4. Setup-Byte Format* BIT NAME 7 (MSB) Setup DESCRIPTION Setup byte always starts with 1. 6 REF/AIN SEL1 5 REF/AIN SEL0 4 INT REF Power Down 3 INT/EXT Clock When [0,0], REF/AIN3 = AIN3, REF = VDD. When [0,1], REF/AIN3 = REF, apply external reference to REF. When [1,0], REF/AIN3 = AIN3, REF = internal reference. When [1,1], REF/AIN3 = REF, REF = internal reference.
PAGE 17
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response HIGH CH1 CH0 10 12/1 D11 (MSB) D10 D9 D8 1 0/1 0/1 0 = 10b 1 = 12b 0/1 0/1 0/1 0/1 START CONDITION ACK D7 D6 D5 D4 D3 D2 D1 D0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 ACK/ NACK R/W ADDRESS START FROM THE MASTER 1 1, CH ADD, 10b/12b FLAG, RESULT (4 MSBs) ACK tACQ ACK RESULT (8 LSBs) ACK STOP tCONV Figure 10.
PAGE 18
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response START ADDRESS FROM THE MASTER 1 ACK 1, CH ADD, 10b/12b RESULT (4 MSBs) ACK tACQ 1, CH ADD, 10b/12b, RESULT (4 MSBs) tACQ ACK RESULT N (8 LSBs) CONVERSION N RESULT (8 LSBs) CONVERSION 1 ACK tACQ ACK tACQ Figure 13.
PAGE 19
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Alarm reset, scan speed, INT_EN , (8 bits) AIN1 thresholds (skip if differential mode, or CS1, CS0 < 1) (24 bits) AIN0 thresholds (24 bits) AIN2 thresholds (skip if CS1, CS0 < 2) (24 bits) AIN3 thresholds (skip if differential mode, or CS1, CS0 < 3) (24 bits) Table 10.
PAGE 20
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Table 13. Readback-Mode Format AIN1 THRESHOLDS AIN0 AIN2 THRESHOLDS (SKIP IF DIFFERENTIAL THRESHOLDS (SKIP IF CS1, CS0 < 2) MODE OR CS1, CS0 < 1) ALARM RESET/SCAN SPEED 1 1 1 1 D2 D1 D0 INT 24 bits 24 bits AIN3 THRESHOLDS (SKIP IF DIFFERENTIAL MODE OR CS1, CS0 < 3) 24 bits 24 bits Table 14.
PAGE 21
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Transfer Functions Output data coding for the MAX1363/MAX1364 is binary in unipolar mode and two’s complement in bipolar mode with 1 LSB = VREF / 2N, where N is the number of bits. Code transitions occur halfway between successive-integer LSB values. Figures 14 and 15 show the transfer functions for unipolar and bipolar operations, respectively.
PAGE 22
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SUPPLIES 3V OR 5V VLOGIC = 3V/5V GND 4.7μF R* = 5Ω 0.1μF VDD GND 3V/5V SNR (MAX)[dB] = 6.02dB x N + 1.
PAGE 23
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Typical Operating Circuit TOP VIEW 3V/5V 0.1μF AIN0 1 10 VDD 9 GND 8 SDA AIN1 2 AIN2 3 AIN3/VREF 4 7 SCL A0 5 6 INT MAX1363 MAX1364 4.7μF VDD AIN0 ANALOG INPUTS AIN1 INT MAX1363 MAX1364 SCL AIN2 2kΩ AIN3/REF *RS GND CREF 0.
PAGE 24
MAX1363/MAX1364 4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PAGE 25
4-Channel, 12-Bit System Monitors with Programmable Trip Window and SMBus Alert Response REVISION NUMBER REVISION DATE 2 3/07 Corrected Table 8 3 3/08 Removed L grade from data sheet DESCRIPTION PAGES CHANGED 17 1, 13, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.