Datasheet

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General Description

The MAX1377/MAX1379/MAX1383 feature two simulta-

neous-sampling, low-power, 12-bit ADCs with serial

interface and internal voltage reference. Fast sampling

rate, low power dissipation, and excellent dynamic per-

formance make the MAX1377/MAX1379/MAX1383

ideal for industrial process control, motor control, and

RF applications.

Conversion results are available through a SPI™-/

QSPI™-/MICROWIRE™-/DSP-compatible interface with

independent serial digital outputs for each channel. The

serial outputs allow twice as much data to be transferred

at the given clock rate. The conversion results for both

ADCs can also be output on a single digital output for

microcontrollers (µCs) and DSPs with only a single serial

input available.

The MAX1377 operates from a 2.7V to 3.6V analog sup-

ply and the MAX1379/MAX1383 operate from a 4.75V

to 5.25V analog supply. A separate 1.8V to AVDD digi-

tal supply allows interfacing to low voltage logic without

the use of level translators.

Two power-down modes, partial and full, allow the

MAX1377/MAX1379 and MAX1383 (full power-down only)

to save power between conversions. Partial power-down

mode reduces the supply current to 2mA while leaving

the reference enabled for quick power-up. Full power-

down mode reduces the supply current to 1µA.

The MAX1377/MAX1379 inputs accept voltages

between zero and the reference voltage or ±V

REF

/2.

The MAX1383 offers an input voltage range of ±10V,

which is ideal for industrial and motor-control applica-

tions. The input to each of the ADCs supports either a

true-differential input or two single-ended inputs.

The MAX1377/MAX1379/MAX1383 are available in a

20-pin TQFN package, and are specified for the automo-

tive (-40°C to +125°C) temperature range.

Applications

Features

♦ Dual, Simultaneous-Sampling, 12-Bit Successive

Approximation Register (SAR) ADCs

♦ 2 x 2 Mux Inputs or Two Differential Inputs

♦ 1.25Msps Sampling Rate per ADC

♦ Internal or External Reference

♦ Excellent Dynamic Performance

70dB SINAD (MAX1377)

71dB SINAD (MAX1379/MAX1383)

84dBc/SFDR

1MHz Full-Linear Bandwidth

♦ 2.7V to 3.6V Low-Power Operation (MAX1377)

50mW (Normal Operation)

6mW (Partial Power-Down)

3µW (Full Power-Down)

♦ 4.75V to 5.25V Low-Power Operation (MAX1379)

90mW (Normal Operation)

10mW (Partial Power-Down)

5µW (Full Power-Down)

♦ 4.75V to 5.25V Low-Power Operation (MAX1383)

280mW (Normal Operation)

2.5µW (Full Power-Down)

♦ 20MHz, SPI-Compatible, 3-Wire Serial Interface

User-Selectable Single (0.625Msps max) or Dual

Outputs (1.25Msps max)

♦ Input Range: ±10V (MAX1383), 0–V

REF

±V

REF

/2 (MAX1377/MAX1379)

♦ Small 20-Pin TQFN Package

MAX1377/MAX1379/MAX1383

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

________________________________________________________________

Maxim Integrated Products

19-4126; Rev 1; 2/09

For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX1377ATP+ -40°C to +125°C 20 TQFN-EP*

MAX1379ATP+ -40°C to +125°C 20 TQFN-EP*

MAX1383ATP+ -40°C to +125°C 20 TQFN-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Motor Control

Communications

Data Acquisition

Bill Validation

Portable Instruments

MUX

12-BIT

SAR

ADC2

REF

REFSEL

RGND

SEL

AGND

DGND

DOUT2

SCLK

CNVST

DOUT1

OUTPUT

BUFFER

OUTPUT

BUFFER

INTERNAL

REFERENCE

CONTROL

LOGIC

SERIAL

INTERFACE

AND TIMING

T/H

AIN1A

AIN1B

AIN2A

AIN2B

T/H

U/B

S/D

AVDD

A = 1

12-BIT

SAR

ADC1

MAX1377

MAX1379

MAX1383

Functional Diagram

Pin Configuration appears at end of data sheet.

Summary of content (25 pages)

PAGE 1
9-4126; Rev 1; 2/09 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface The MAX1377/MAX1379/MAX1383 feature two simultaneous-sampling, low-power, 12-bit ADCs with serial interface and internal voltage reference. Fast sampling rate, low power dissipation, and excellent dynamic performance make the MAX1377/MAX1379/MAX1383 ideal for industrial process control, motor control, and RF applications.
PAGE 2
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................-0.3V to +6V VL to DGND ..............................................................-0.3V to +6V SCLK, CS, CNVST, U/B, S/D, SEL, REFSEL to DGND.......................................-0.3V to (VL + 0.3V) DOUT_ to DGND ...........................................-0.3V to (VL + 0.
PAGE 3
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface (VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX1377 (continued) (VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface (VAVDD = 4.75V to 5.25V, VL = 3V, fSCLK = 20MHz (50% duty cycle), VREF = 4.096V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX1379 (continued) (VAVDD = 4.75V to 5.25V, VL = 3V, fSCLK = 20MHz (50% duty cycle), VREF = 4.096V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface (VAVDD = 4.75V to 5.25V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.50V, REFSEL = VL, S/D = DGND, CREF = 1µF; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 8
TIMING CHARACTERISTICS (Figures 6, 10) VAVDD = 4.25V to 5.25V, VL = 1.8V to AVDD, VREF = 4.096V, fSCLK = 20MHz for MAX1379, 50% duty cycle, CL = 30pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL SCLK Clock Period CONDITIONS MIN TYP tCP 50 tCH/tCL 45 SCLK Pulse-Width High tCH 22.5 SCLK Pulse-Width Low tCL 22.
PAGE 9
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface MAX1377 UNIPOLAR FFT -80 -60 -100 -100 100 200 300 400 500 300 400 500 600 0 0.8 0.6 0.2 INL (LSB) 0.4 0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE MAX1377 BIPOLAR DNL vs. DIGITAL OUTPUT CODE MAX1379 UNIPOLAR INL vs.
PAGE 10
Typical Operating Characteristics (continued) (VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.) MAX1379 BIPOLAR DNL vs. DIGITAL OUTPUT CODE 0.8 0.6 0.2 0.2 0 -0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 2048 0 4096 3072 MAX1379 GAIN ERROR vs. TEMPERATURE 3072 4096 -40 1.2 CHANNEL 1 0.8 0.4 -40 -60 35 60 -80 85 fSAMPLE = 1.8Msps fSCLK = 28.8MHz fIN = 250kHz SINAD = 70.05dB SNR = 70.32dB THD = -82.35dB SFDR = 83.22dB VREF = 4.
PAGE 11
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface MAX1379 AVDD FULL POWER-DOWN CURRENT vs. TEMPERATURE 0.8 AVDD FULL POWER-DOWN CURRENT (mA) 0.9 0.7 0.6 -60 0.5 0.4 -80 0.3 0.2 -100 0.1 -120 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 0 300 600 900 -40 -25 -10 ANALOG INPUT FREQUENCY (kHz) 5 20 35 50 65 -40 -25 -10 80 13.0 12.5 12.0 11.5 11.0 35 50 65 80 MAX1377 toc26 20 18 AVDD SUPPLY CURRENT (mA) 13.5 20 MAX1379 AVDD SUPPLY CURRENT vs.
PAGE 12
Typical Operating Characteristics (continued) (VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.) 0.8 0.6 0.8 0.6 0.4 0.2 0.2 0.2 -0.2 INL (LSB) 0.4 DNL (LSB) 0.4 0 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 -1.0 1024 2048 3072 0 4096 1024 2048 3072 0 4096 1024 2048 3072 DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE MAX1383 UNIPOLAR DNL vs. DIGITAL OUTPUT CODE MAX1383 OFFSET ERROR vs.
PAGE 13
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface CONVERTING AT 1.25Msps 50 48 STATIC 46 42 54 53 52 50 -1 -2 500 1000 1500 2000 10 CONVERSION RATE (kHz) FREQUENCY (MHz) MAX1383 AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1383 AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1383 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE 50 CONVERTING AT 1.25Msps 48 STATIC 46 44 50 CONVERTING AT 1.25Msps 48 46 STATIC 44 4.65 4.85 5.05 5.25 TEMPERATURE AT TA = -40°C 2.
PAGE 14
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface MAX1377/MAX1379/MAX1383 Pin Description 14 PIN NAME FUNCTION 1 REFSEL 2 REF Internal Reference Output/External Reference Input. For internal reference mode, bypass REF to RGND with a ≥ 1µF capacitor. For external reference mode, apply a reference voltage at REF. 3 RGND Reference Ground/Common Negative Input. In bipolar mode, RGND is the reference ground.
PAGE 15
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface The MAX1377/MAX1379/MAX1383 use an input track and hold (T/H) and SAR circuitry to convert an analog input signal to a digital 12-bit output. The dual serial interface requires a minimum of three digital lines (SCLK, CNVST, and DOUT) and provides easy interfacing to microprocessors (µPs) and DSPs. Four digital lines are required for dual-output mode.
PAGE 16
the MAX1383, the signal bandwidth is limited to 100kHz by specification. Since ±10V signals are divided down to a 2.5V range, this version should only be used with signals greater than 5V. For those applications with signals 5V or less, use the MAX1377/MAX1379 for best SNR performance. The configuration is shown on Figure 3b.
PAGE 17
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface Initialization After Power-Up Upon initial power-up, the MAX1377/MAX1379/ MAX1383 require a complete conversion cycle to initialize the internal calibration. Following this initialization, the ADC is ready for normal operation. This initialization is only required after a hardware power-on reset and is not required after exiting partial or full power-down mode.
PAGE 18
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface CS CNVST POWER-DOWN 1 SCLK 3 2 4 CONTINUOUS MODE 16 15 14 DOUT_ HI-Z 17 DOUT_ HI-Z Figure 8.
PAGE 19
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface Partial Power-Down (PPD) Reduce power consumption by placing the MAX1377/ MAX1379 in partial power-down mode. Partial powerdown mode is ideal for infrequent data sampling and applications requiring fast wake-up times. Pull CNVST high after the 3rd and before the 14th rising edge of SCLK to place the device in partial power-down mode. This reduces the analog supply current to 2mA.
PAGE 20
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface PPD WINDOW CNVST CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE SCLK 3 1 9 1ST SCLK RISING EDGE 0 DOUT_ 0 0 MODE 14 DOUT_ GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH D11 D10 D9 D8 D7 NORMAL PARTIAL POWER-DOWN ENABLED REF Figure 11.
PAGE 21
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface QSPI Unlike SPI, which requires two 8-bit reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1377/MAX1379/MAX1383 require 16 clock cycles from the µC to clock out the 12 bits of data. The conversion result contains three zeros followed by the 12 data bits, and a trailing zero with the data in the MSB-first format.
PAGE 22
MAX1377/MAX1379/MAX1383 Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface MAX1383 AIN1A MISO1 12-BIT ADC T/H MISO2 12-BIT ADC T/H DSP-BASED DIGITAL PROCESSING ENGINE AIN1B AIN2A AIN2B IGBT CURRENT DRIVERS CURRENT SENSORS IPHASE2 IPHASE1 THREE-PHASE ELECTRIC MOTOR PHASE 2 PHASE 1 PHASE 3 SIN/COS POSITION RESOLVER IPHASE3 = - IPHASE1 - IPHASE2 Figure 16.
PAGE 23
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface AVDD VL MAX1377 I QUADRATURE DEMODULATOR Q Establish a single-point analog ground (star ground point) at AGND, separate from the digital ground, DGND. Connect all other analog grounds and DGND to this star ground point for further noise reduction. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. See Figure 14.
PAGE 24
Intermodulation Distortion zation noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are input into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2.
PAGE 25
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface PAGES CHANGED REVISION NUMBER REVISION DATE 0 7/08 Initial release of the MAX1377/MAX1379 — 1 2/09 Initial release of the MAX1383 — DESCRIPTION Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.