Datasheet
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
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The internal reference is continuously powered-up dur-
ing both normal and partial power-down modes. In full
power-down mode, the internal reference is disabled.
Allow at least 2ms recovery time after a power-on reset
or exiting full power-down mode for the reference to
settle to its intended value.
Input Voltage Range (MAX1383)
The input range on the MAX1383 has an 8x relationship
with the reference voltage. For example, when the refer-
ence voltage (internal or external) is 2.5V, the input
range is ±10V (20V
P-P
).
External Reference Mode
Drive REFSEL high to select external reference mode.
Apply a reference voltage at REF. Bypass REF with
a 10nF capacitor and a 4.7µF capacitor to RGND. As
with the internal reference, it is important to select a low
ESR capacitor and keep the trace resistance as low
as possible.
Serial Interface
Initialization After Power-Up
Upon initial power-up, the MAX1377/MAX1379/ MAX1383
require a complete conversion cycle to initialize the inter-
nal calibration. Following this initialization, the ADC is
ready for normal operation. This initialization is only
required after a hardware power-on reset and is not
required after exiting partial or full power-down mode.
Starting a Conversion and Reading the Output
With SCLK idling high or low, a falling edge on CNVST
begins a conversion (see Figure 6). This causes the
analog input stage to transition from track to hold
mode. SCLK provides the timing for the conversion
process, and data is shifted out as each bit of the result
is determined. A rising edge in CNVST forces the
device into one of three modes. The mode is deter-
mined by the clock cycle in which the transition occurs
and whether the device is set for single or dual outputs.
Figures 7 and 8 show each mode that is activated with
a rising CNVST edge for single and dual outputs.
CNVST
SCLK
DOUT_
t
SETUP
t
CL
t
CH
t
DHOLD
t
DOUT
t
CSW
CS
t
ACQ
D11 D10
D9
D8
D7
D6
D5
D4
D3
14
13
1
t
CST
TRACKING
HOLD MODE
INTERNAL T/H STATE
D2
D1
D0
Figure 6. Detailed Serial-Interface Timing Diagram
CNVST
SCLK
1
2
3
4
14
28
POWER-DOWN CONTINUOUS MODE
DOUT1 GOES HI-Z
DOUT1 HI-Z
29
CS
Figure 7. Single-Output CNVST Transition Modes