Datasheet
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
18 ______________________________________________________________________________________
DOUT1 (and DOUT2, if S/D = low) transitions from high
impedance to being actively driven low once the ADC
enters hold mode. DOUT_ remains low for the first three
SCLK pulses and begins outputting the conversion result
after the 4th rising edge of SCLK, MSB first. DOUT_ tran-
sitions complete t
DOUT
after each SCLK rising edge and
the DOUT_ values remain valid for t
HOLD
after the next
rising edge of SCLK. A total of 16 SCLK pulses are
required to complete a normal conversion in dual-output
mode and 28 SCLK pulses in single-output mode.
DOUT_ goes low after the 16th rising edge of SCLK and
goes high-impedance when CNVST goes high.
For continuous operation in single-output mode, pull
CNVST high after the 14th rising and before the 28th
rising edge of SCLK. In dual-output mode, if CNVST
returns high after the 14th rising and before the 16th
falling edge of SCLK, DOUT_ remains active so continu-
ous conversions can be sustained. If CNVST is low
during the 16th edge of SCLK (dual-conversion mode)
and the 28th falling edge of SCLK (single-output mode),
DOUT_ returns to its high-impedance state on the next
rising edge of CNVST or SCLK, enabling the serial inter-
face to be shared by multiple devices. See Figures 9
and 10 for single and continuous conversion timing
diagrams.
CNVST
SCLK
DOUT_
D11 D10
D9
D8
D7
D6
D5
D4
00
0
SINGLE CONVERSION
1
D3
D2
D1
D0
16
9
8
HIGH-Z
SCLK
DOUT_
D11 D10
D9
D8
D7
D6
D5
D4
00
0
1
D3
D2
D1
D0
1614
9
8
1
CNVST
CONTINUOUS CONVERSION
CONTINUOUS-CONVERSION
SELECTION WINDOW*
*CNVST MUST GO HIGH BETWEEN THE 14TH RISING AND 16TH FALLING EDGES OF SCLK.
TO MAINTAIN CONTINUOUS CONVERSIONS, DOUT_ REMAINS LOW BETWEEN
CONVERSION RESULTS IN CONTINUOUS-CONVERSION DUAL-OUTPUT MODE.
HIGH-Z
Figure 9. Dual-Output Mode, Single and Continuous Conversions
CNVST
SCLK
1
2
3
4
14
POWER-DOWN CONTINUOUS MODE
DOUT_ HI-Z
DOUT_ HI-Z
15
16 17
CS
Figure 8. Dual-Output CNVST Transition Modes