Datasheet

MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
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For CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA =
1, the data is clocked into the µC on the rising edge of
SCLK. For CPOL = 0 and CPHA = 1 or CPOL = 1 and
CPHA = 0, the data is clocked into the µC on the falling
edge of SCLK. The MAX1377/MAX1379/MAX1383 are
compatible with all CPOL/CPHA configurations since
the data is valid on the falling and rising edge of SCLK.
QSPI
Unlike SPI, which requires two 8-bit reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1377/MAX1379/MAX1383 require 16
clock cycles from the µC to clock out the 12 bits of
data. The conversion result contains three zeros fol-
lowed by the 12 data bits, and a trailing zero with the
data in the MSB-first format.
Three-Phase Motor Controller
The MAX1377/MAX1379/MAX1383 are ideally suited for
motor-control systems (Figure 16). The devices’ simulta-
neously sampled inputs eliminate the need for complicat-
ed DSP algorithms that realign sequentially sampled
data into a simultaneous sample set. The ±10V
(MAX1383) input allows for standard industrial inputs,
eliminating the need for voltage-scaling amplifiers.
MAX1377
MAX1379
MAX1383
I/O
SCK
MISO1
MISO2
SS
3V TO 5V
CNVST
SCLK
DOUT1
DOUT2
MAX1377
MAX1379
MAX1383
SCK
MISO1
MISO2
SS
3V TO 5V
CNVST
SCLK
DOUT1
DOUT2
MAX1377
MAX1379
MAX1383
I/O
SK
SI1
SI2
CNVST
SCLK
DOUT1
DOUT2
A) SPI
B) QSPI
C) MICROWIRE
CS
Figure 15. Common Serial-Interface Connections to the
MAX1377/MAX1379/MAX1383
SUPPLIES
AVDD
AGND DGND
V
DD
DIGITAL
CIRCUITRY
OPTIONAL
FERRITE
BEAD
ANALOG
SUPPLY
RETURN RETURN
DIGITAL
SUPPLY
V
L
GND
MAX1377
MAX1379
MAX1383
Figure 14. Power-Supply Grounding and Bypassing
SCLK
DOUT_
t
DHOLD
t
DOUT
Figure 13. Data Valid and Hold Times