Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - power management - special purpose 4.5 mA TQFN 48 (7x7)

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX1385/MAX1386 set and control bias conditions

for dual RF LDMOS power devices found in cellular

base stations. Each device includes a high-side cur-

rent-sense amplifier with programmable gains of 2, 10,

and 25 to monitor LDMOS drain current over the 20mA

to 5A range. Two external diode-connected transistors

monitor LDMOS temperatures while an internal temper-

ature sensor measures the local die temperature of the

MAX1385/MAX1386. A 12-bit ADC converts the pro-

grammable-gain amplifier (PGA) outputs, external/inter-

nal temperature readings, and two auxiliary inputs.

The two gate-drive channels, each consisting of 8-bit

coarse and 10-bit fine DACs and a gate-drive amplifier,

generate a positive gate voltage to bias the LDMOS

devices. The MAX1385 includes a gate-drive amplifier

with a gain of 2 and the MAX1386 gate-drive amplifier

provides a gain of 4. The 8-bit coarse and 10-bit fine

DACs allow up to 18 bits of resolution. The MAX1385/

MAX1386 include autocalibration features to minimize

error over time, temperature, and supply voltage.

The MAX1385/MAX1386 feature an I

C/SPI™-compatible

serial interface. Both devices operate from a 4.75V to

5.25V analog supply (3.2mA supply current), a 2.7V to

5.25V digital supply (3.1mA supply current), and a 4.75V

to 11.0V gate-drive supply (4.5mA supply current). The

MAX1385/MAX1386 are available in a 48-pin thin QFN

package.

Applications

RF LDMOS Bias Control in Cellular Base Stations

Industrial Process Control

Features

♦ Integrated High-Side Drain Current-Sense PGA

with Gain of 2, 10, or 25

♦ ±0.5% Accuracy for Sense Voltage Between 75mV

and 250mV

♦ Full-Scale Sense Voltage of 100mV with Gain of 25

♦ Full-Scale Sense Voltage of 250mV with Gain of 10

♦ Common-Mode Range of 5V to 30V Drain Voltage

for LDMOS

♦ Adjustable Low Noise 0 to 5V, 0 to 10V Output

Gate-Bias Voltage Ranges with ±10mA Gate Drive

♦ Fast Clamp to 0V for LDMOS Protection

♦ 8-Bit DAC Control of Gate-Bias Voltage

♦ 10-Bit DAC Control of Gate-Bias Offset with

Temperature

♦ Internal Die Temperature Measurement

♦ External Temperature Measurement by Diode-

Connected Transistor (2N3904)

♦ Internal 12-Bit ADC Measurement of Temperature,

Current, and Voltages

♦ Selectable I

C-/SPI-Compatible Serial Interface

400kHz/1.7MHz/3.4MHz I

C-Compatible Control

for Settings and Data Measurement

16MHz SPI-Compatible Control for Settings

and Data Measurement

♦ Internal 2.5V Reference

♦ Three Address Inputs to Control Eight Devices in

C Mode

MAX1385/MAX1386

Dual RF LDMOS Bias Controllers

with I

C/SPI Interface

________________________________________________________________

Maxim Integrated Products

19-4456; Rev 0; 2/09

EVALUATION KIT

AVAILABLE

Ordering Information/Selector Guide

PART TEMP RANGE PIN-PACKAGE TEMP ERROR (°C) V

GATE

(V)

MAX1385AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 5

MAX1385BETM+ -40°C to +85°C 48 Thin QFN-EP* ±2 5

MAX1386AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 10

MAX1386BETM+** -40°C to +85°C 48 Thin QFN-EP* ±2 10

SPI is a trademark of Motorola, Inc.

EP = Exposed pad.

Future product—contact factory for availability.

Denotes a lead(Pb)-free/RoHS-compliant package.

Pin Configuration and Typical Operating Circuit (I

C Mode)

appear at end of data sheet.

Summary of content (52 pages)

PAGE 1
9-4456; Rev 0; 2/09 KIT ATION EVALU LE B A IL A AV Dual RF LDMOS Bias Controllers with I2C/SPI Interface Features The MAX1385/MAX1386 set and control bias conditions for dual RF LDMOS power devices found in cellular base stations. Each device includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor LDMOS drain current over the 20mA to 5A range.
PAGE 2
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface ABSOLUTE MAXIMUM RATINGS Digital Inputs to DGND ............-0.3V to the lower of +6V and (DVDD + 0.3V) SDA/DIN, SCL to DGND...........................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Maximum Continuous Current into Any Pin ........................50mA Continuous Power Dissipation (TA = +70°C) 48-Pin, 7mm x 7mm, Thin QFN (derate 27.8 mW/°C above +70°C)...................
PAGE 3
Dual RF LDMOS Bias Controllers with I2C/SPI Interface (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface ELECTRICAL CHARACTERISTICS (continued) (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Channel-to-Channel Offset Matching ±0.1 LSB Channel-to-Channel Gain Matching ±0.
PAGE 5
Dual RF LDMOS Bias Controllers with I2C/SPI Interface (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface ELECTRICAL CHARACTERISTICS (continued) (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
Dual RF LDMOS Bias Controllers with I2C/SPI Interface (GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz Serial-Clock Frequency fSCL 0 Bus Free Time Between STOP and START Condition tBUF 1.3 µs 0.
PAGE 8
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface I2C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2) (GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted). PARAMETER Serial-Clock Frequency SYMBOL CONDITIONS MIN TYP MAX UNITS 3.
PAGE 9
Dual RF LDMOS Bias Controllers with I2C/SPI Interface (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Period tCP 62.
PAGE 10
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface SDA tF tLOW t SU;DAT tR tF t HD;STA tSP tr tBUF SCL t HD;STA t HIGH t HD;DAT S t SU;STO t SU;STA Sr S P Figure 1. I2C Slow-/Fast-Mode Timing Diagram Sr Sr P t RDA t FDA SDA t SU;STA t HD;DAT t HD;STA t SU;STO t SU;DAT SCL t FCL t RCL1 t HIGH t LOW t RCL t LOW t RCL1 t HIGH Figure 2.
PAGE 11
Dual RF LDMOS Bias Controllers with I2C/SPI Interface 3.5 TA = +25°C 3.4 3.3 TA = -40°C 3.2 3.1 3.0 4.7 4.8 4.9 5.0 5.1 5.2 2.50 2.25 1.50 1.25 1.00 4.1 4.0 3.2 3.7 4.7 4 5.2 AvPGA = 2 CMV = 12V 0.45 0.40 0.35 0.30 0.25 0.20 0.15 35 50 65 9 10 11 -1.5 -2.0 -2.5 0.05 -3.5 -4.0 0 250 500 750 1000 1250 0 20 40 60 80 VSENSE (mV) VSENSE (mV) TOTAL PGAOUT_ ERROR vs. COMMON-MODE VOLTAGE PGAOUT_ OFFSET VOLTAGE vs.
PAGE 12
Typical Operating Characteristics (continued) (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = +25°C, unless otherwise noted.) PGAOUT_ 0mV TO 250mV VSENSE TRANSIENT RESPONSE PGAOUT_ PEDESTAL ERROR DURING CALIBRATION MAX1385/86 toc10 GATE_ OFFSET COMPENSATED ERROR vs.
PAGE 13
Dual RF LDMOS Bias Controllers with I2C/SPI Interface INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (8-BIT COARSE DAC) 0.8 1.0 0.6 0.8 0.6 0.4 0.2 0.2 0.2 -0.2 DNL (LSB) 0.4 INL (LSB) 0.4 0 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 150 200 250 -1.0 0 200 DIGITAL INPUT CODE 400 600 800 0 1000 50 DIGITAL INPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (10-BIT FINE DAC) 0.6 1.0 0.8 0.6 0.4 0.2 0.2 INL (LSB) 0.4 0 -0.
PAGE 14
Typical Operating Characteristics (continued) (GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA = +25°C, unless otherwise noted.) INTERNAL REFERENCE vs. TEMPERATURE ADC OFFSET ERROR vs. TEMPERATURE AVDD = 5V 0.075 0.050 OFFSET ERROR (%) 2.499 2.494 MAX1385/86 toc26 AVDD = 5V 2.504 REFERENCE VOLTAGE (V) 0.100 MAX1385/86 toc25 2.509 0.025 0 -0.025 -0.050 2.489 -0.075 2.484 -0.
PAGE 15
Dual RF LDMOS Bias Controllers with I2C/SPI Interface PIN NAME FUNCTION 1 DGND Digital Ground 2 SAFE1 Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when programmed channel 1 temperature threshold or current threshold has been reached. 3 A0/CSB I2C-Compatible Address 0/ SPI-Compatible Chip Select. See the Digital Serial Interface section. In SPI mode, drive A0/CSB low to select the device. 4 CNVST Active-Low Conversion-Start Input.
PAGE 16
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Pin Description (continued) 16 PIN NAME 23 GATEGND Gate-Drive Amplifier Ground FUNCTION 24 GATEVDD Gate-Drive Amplifier Supply Input 26 OPSAFE2 Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND. 27 CS2+ Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2 supply. 29 CS2- Current-Sense Negative Input 2.
PAGE 17
Dual RF LDMOS Bias Controllers with I2C/SPI Interface SAFE2 SAFE1 AVDD ALARM DIGITAL CURRENT AND TEMPERATURE COMPARATORS DVDD PGAOUT1 CS1+ PGA1 DGND CS1PGA REGISTERS CS2SCL PGA2 CS2+ SDA/DIN SERIAL INTERFACE A0/CSB REGISTER SECTION PGAOUT2 A1/DOUT A2/N.C.
PAGE 18
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface Detailed Description The MAX1385/MAX1386 set and control bias conditions for dual RF LDMOS power devices found in cellular base stations. Each device includes a high-side current-sense amplifier with programmable gains of 2, 10, and 25 to monitor the LDMOS drain current over the 20mA to 5A range.
PAGE 19
Dual RF LDMOS Bias Controllers with I2C/SPI Interface Clock Mode 01 In clock mode 01, power-up, acquisition, conversion, and power-down are all initiated by setting CNVST low for at least 40ns. Conversions are performed automatically using the internal oscillator. The ADC sets the BUSY output high, powers up, scans all requested channels, stores the results in the FIFO, and then powers down.
PAGE 20
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface CAPACITIVE DAC ADCIN_ CONTROL LOGIC AGND TRACK MODE CAPACITIVE DAC ADCIN_ CONTROL LOGIC AGND HOLD/CONVERSION MODE Figure 4. Equivalent ADC Input Circuit Analog Input Track and Hold The equivalent circuit (Figure 4) shows the MAX1385/MAX1386 ADC input architecture. In track mode, a positive input capacitor is connected to ADCIN_ and a negative input capacitor is connected to AGND.
PAGE 21
Dual RF LDMOS Bias Controllers with I2C/SPI Interface DAC Description The MAX1385/MAX1386 include two 8-bit and 10-bit DAC blocks to independently control the voltage on each LDMOS gate. Both 10-bit and 8-bit DACs can be automatically calibrated to minimize output error over time, temperature, and supply voltage.
PAGE 22
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface HIGH-CAL COARSE DAC_ HIGH WIPER OUTPUT REGISTER INPUT REGISTERS HIWIPE_ REGISTER HCAL VDACREF THRUHI_ REGISTER TO 10-BIT FINE DAC THRULO_ REGISTER LOWIPE_ REGISTER COARSE DAC_ LOW WIPER OUTPUT REGISTER LCAL LOW-CAL LOAD DAC CONTROL REGISTER (LDAC) Figure 5.
PAGE 23
Dual RF LDMOS Bias Controllers with I2C/SPI Interface Temperature Measurements The MAX1385/MAX1386 measure the internal die temperature and two external remote-diode temperature sensors. Set up a temperature conversion by writing to the Analog-to-Digital Conversion register (see the ADCCON (Write) section). Optionally program SAFE1 and SAFE2 outputs to depend on programmed temperature thresholds. The MAX1385/MAX1386 can perform temperature measurements with an internal diode-connected transistor.
PAGE 24
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface HIGHEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR HIGH THRESHOLD REGISTER) ALARM OUTPUT DEASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL* ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL HIGH THRESHOLD BUILT-IN 8 TO 64 LSBs OF HYSTERESIS RANGE OF VALUES THAT DO NOT CAUSE AN ALARM BUILT-IN 8 TO 64 LSBs OF HYSTERESIS ALARM OUTPUT ASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL *ONLY WHEN ALARM IS CONFIGURED F
PAGE 25
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD BUILT-IN HYSTERESIS BUILT-IN HYSTERESIS LOW THRESHOLD TIME ALARM OUTPUT OUTPUTCOMPARATOR MODE (ACTIVE LOW) OUTPUTINTERRUPT MODE (ACTIVE LOW) FLAG REGISTER READ FLAG REGISTER FLAG REGISTER READ READ TIME Figure 8.
PAGE 26
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface HIGHEST POSSIBLE THRESHOLD VALUE (DEFAULT VALUE FOR HIGH THRESHOLD REGISTER) ALARM OUTPUT ASSERTED WHEN MEASURED VALUE RISES ABOVE THIS LEVEL HIGH THRESHOLD ALARM OUTPUT ASSERTED WHEN MEASURED VALUE FALLS BELOW THIS LEVEL LOW THRESHOLD RANGE OF VALUES THAT DO NOT CAUSE AN ALARM *ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE. WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ FOR ALARM TO BE DEASSERTED.
PAGE 27
Dual RF LDMOS Bias Controllers with I2C/SPI Interface REGISTER DESCRIPTION Analog-to-Digital Conversion MNEMONIC ADCCON HEX COMMAND WRITE READ 62 — Channel 1 High-Current Threshold IH1 24 A4 Channel 1 High-Temperature Threshold TH1 20 A0 Channel 1 Low-Current Threshold IL1 26 A6 Channel 1 Low-Temperature Threshold TL1 22 A2 Channel 2 High-Current Threshold IH2 2C AC Channel 2 High-Temperature Threshold TH2 28 A8 Channel 2 Low-Current Threshold IL2 2E AE Channel 2 Low-Tempe
PAGE 28
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface MEASUREMENT VALUE (TEMPERATURE OR CURRENT) HIGH THRESHOLD LOW THRESHOLD TIME ALARM OUTPUT OUTPUTCOMPARATOR MODE (ACTIVE LOW) OUTPUTINTERRUPT MODE (ACTIVE LOW) FLAG REGISTER READ FLAG REGISTER READ TIME Figure 10. Hysteresis-Threshold-Mode Timing Diagram Table 3.
PAGE 29
Dual RF LDMOS Bias Controllers with I2C/SPI Interface D15 D14 D13 D12 D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) POR X X X X 1 0 0 0 0 0 0 0 0 0 0 0 Bit Value (°C) X X X X -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125 X = Don’t care. Table 5.
PAGE 30
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface Table 7. DCFIG (Read/Write) Table 7a. Gain-Setting Modes BIT NAME DATA BIT POR PG_SET1 PG_SET0 X D15–D10 X Don’t care FUNCTION 0 0 PGA_ gain of 2 PG2SET1 D9 0 PGA 2 gain-setting 0 1 PGA_ gain of 10 PG2SET0 D8 0 PGA 2 gain-setting 1 X PGA_ gain of 25 PG1SET1 D7 0 PGA 1 gain-setting X = Don’t care.
PAGE 31
Dual RF LDMOS Bias Controllers with I2C/SPI Interface REFDAC1 REFDAC0 DESCRIPTION 0 X External. Bypass REFDAC with a 0.1µF capacitor to AGND. 1 0 Internal. Leave REFDAC unconnected. 1 1 Internal. Connect a 0.1µF capacitor to REFDAC for extra decoupling and better noise performance. X = Don’t care. DAC input register is transferred to the appropriate DAC output register.
PAGE 32
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface Table 8.
PAGE 33
Dual RF LDMOS Bias Controllers with I2C/SPI Interface BIT NAME DATA BIT POR FUNCTION LCAL D15 1 1 = Low wiper autocalibration. 0 = No low wiper autocalibration. — D14–D8 X Don’t care. — D7–D0 0000 0000 8-bit coarse low wiper DAC input code. D7 is the MSB. ALMHCFG (Read/Write) The Hardware Alarm Configuration register controls SAFE1, SAFE2, and ALARM outputs.
PAGE 34
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface TEXT2 to 1 to select the temperature at external diode 2 to be converted. Set ADCSEL1 to 1 to select voltages at ADCIN1 to be converted. Set IEXT1 to 1 to select voltages at PGAOUT1 to be converted. Set TEXT1 to 1 to select the temperature at external diode 1 to be converted. Set TINT to 1 to select the internal temperature of the MAX1385/MAX1386 to be converted.
PAGE 35
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 16.
PAGE 36
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface Table 17.
PAGE 37
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 19.
PAGE 38
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface FIFOOVER is set to 1 when the FIFO overflows. FIFOOVER is set to 0 after reading the Flag register. All threshold-related bits in the Flag register can be cleared at once by writing to the ALMSCLR bit in the Software Alarm Configuration register (see the ALMSCFG (Read/Write) section). HIGHI2 is set to 1 when the channel 2 current exceeds its high threshold. HIGHI2 resets to 0 after reading the Flag register.
PAGE 39
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 23.
PAGE 40
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface WRITE WORD FORMAT S OR Sr ADDRESS R/W 7 BITS 0 ACK WRITE COMMAND ACK DATA ACK ACK Sr OR P 8 BITS (LSB) 8 BITS (MSB) 8 BITS DATA WRITE BLOCK FORMAT S OR Sr ADDRESS R/W 7 BITS 0 ACK WRITE COMMAND ACK DATA ACK ACK Sr OR P 8 BITS (LSB) 8 BITS (MSB) 8 BITS DATA N 3-BYTE SEQUENCES (S, Sr, AND P NOT NEEDED) 5-BYTE READ S OR Sr ADDRESS R/W 7 BITS 0 ACK READ COMMAND ACK 8 BITS Sr ADDRESS R/W 7 BITS 1
PAGE 41
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 25.
PAGE 42
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface S OR Sr Sr ADDRESS R/W 7 BITS 0 ADDRESS R/W 7 BITS 1 ACK WRITE COMMAND ACK 8 BITS ACK DATA ACK 8 BITS (MSB) ACK DATA 8 BITS (LSB) 8 BITS (MSB) DATA ACK DATA NACK Sr OR P 8 BITS (LSB) Figure 12.
PAGE 43
Dual RF LDMOS Bias Controllers with I2C/SPI Interface C7 C6 C5 C4 C3 C2 C1 C0 ACK SCL 1 2 3 4 5 6 7 8 9 MAX1385/MAX1386 SDA Figure 15. Command Byte SDA D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK OR ACK SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Figure 16. Data Bytes S Sr P SDA SCL Figure 17. START and STOP Conditions high-speed mode (HS mode), allowing bus speeds up to 3.4MHz.
PAGE 44
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface A RISING EDGE OF CSB DURING THIS PERIOD COMPLETES A VALID WRITE COMMAND. CSB SCL DIN CR/W C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 18. SPI Write Format CSB SCL DIN CR/W C6 C5 C4 C3 C2 C1 C0 D15 DOUT D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 19. SPI Read Format S NOT ACKNOWLEDGE SDA ACKNOWLEDGE SCL 1 2 8 9 Figure 20.
PAGE 45
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 HS-MODE MASTER CODE S 0 0 0 0 X 1 X A X Sr SDA SCL HS MODE FS MODE Figure 21. Changing to HS Mode MASTER TO SLAVE SLAVE TO MASTER S MASTER CODE FS MODE FS MODE FS MODE A Sr SLAVE ADDRESS R/W A COMMAND/DATA A P N BYTES PLUS ACK HS MODE CONTINUES Sr SLAVE ADD HS MODE CAN ALSO BE CONTINUED WITH A COMMAND BYTE Figure 22.
PAGE 46
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface tCNV11 tACQ11 tACQ11 CNVST IDLE, BUT REF AND TEMP SENSOR STAY POWERED UP TEMP CONVERSION IN ~40µs INTERNAL TEMPERATURE CONVERSION RESULT IS STORED IN FIFO USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER TO SET UP CONVERSION SCAN OF INTERNAL TEMPERATURE, PGAOUT1, AND ADCIN1 IDLE, BUT REF AND TEMP SENSOR STAY POWERED UP 2µs ACQUISITION FOR ADCIN1 5.
PAGE 47
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 27. Basic Software Initialization COMMAND BYTE DATA WORD 0x64 0x0008 DESCRIPTION Bring the device out of shutdown mode. 0x64 0x0008 Set internal reference and both DAC channels on. 0x20 0x02A8 Set the channel 1 high-temperature threshold to +85°C. 0x22 0x0EC0 Set the channel 1 low-temperature threshold to -40°C. 0x24 0x02C1 Set the channel 1 high-current threshold to 4.3A for 50mΩ RSENSE, AvPGA = 2, and VREFADC = 2.
PAGE 48
Table 28. DAC Write Commands Without Autocalibration ACTION REQUIRED RECOMMENDED COMMAND SEQUENCE OTHER POSSIBLE COMMAND SEQUENCES Update fine DAC_ without triggering autocalibration. Write to FINE_. Write to LDAC to update fine DAC_. Write to FINETHRU_ to immediately update fine DAC_. Update high wiper coarse DAC_ without triggering autocalibration. Write to HIWIPE_ with HCAL set to 0. Write to LDAC to update high wiper coarse DAC_. Write to THRUHI_ to immediately update high wiper coarse DAC_.
PAGE 49
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Table 29. DAC Write Commands with Autocalibration ACTION REQUIRED RECOMMENDED COMMAND SEQUENCE OTHER POSSIBLE COMMAND SEQUENCES Update fine DAC_ and trigger autocalibration. Write to FINECAL_. Autocalibration begins after writing to FINECAL_. Write to LDAC to update fine DAC_. Write to FINECALTHRU_ to immediately update fine DAC_. Update high wiper coarse DAC_ and trigger autocalibration. Write to HIWIPE_ with HCAL set to 1.
PAGE 50
Dual RF LDMOS Bias Controllers with I2C/SPI Interface MAX1385/MAX1386 Typical Operating Circuit (I2C Mode) 5V 5V EXTERNAL REFERENCE SCL DVDD SCL SDA SDA/DIN GATEVDD REFDAC REFADC AVDD DRAIN SUPPLY CS1+ ALARM C F* MICROCONTROLLER BUSY RF* CS1- SAFE2 SAFE1 +5V GATE1 A0/CSB A1/DOUT MAX1385 MAX1386 DGND RF OUTPUT A2/N.C.
PAGE 51
Dual RF LDMOS Bias Controllers with I2C/SPI Interface N.C. CS2+ OPSAFE2 N.C. GATE2 CS2- GATE1 OPSAFE1 CS1+ CS1- N.C. N.C. TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 N.C. 37 24 GATEVDD N.C. N.C. 38 23 39 22 GATEGND AGND 40 21 41 20 PGAOUT1 A2/N.C. N.C. SCL SDA/DIN A1/DOUT 42 19 MAX1385 MAX1386 43 44 18 13 DXP2 N.C. BUSY 46 15 DVDD 48 6 7 8 DOCUMENT NO. 48 TQFN-EP T4877-6 21-0044 9 10 11 12 DXN1 5 REFDAC REFADC DXP1 4 SAFE2 N.C.
PAGE 52
MAX1385/MAX1386 Dual RF LDMOS Bias Controllers with I2C/SPI Interface Appendix: Recommended Power-Up Code Sequence The following section shows the recommended startup code for the MAX1385. This code ensures clean startup of the part, irrespective of power-supply ramp speed and starts the device regulating to 312.5mV on both channels. Change the THRUDAC writes to change the voltage across the sense resistor. Note it should be run after the power supplies have stabilized.