Datasheet

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MAX1401

+3V, 18-Bit, Low-Power, Multichannel,

Oversampling (Sigma-Delta) ADC

________________________________________________________________ Maxim Integrated Products 1

19-1480; Rev 1; 7/02

EVALUATION KIT

AVAILABLE

General Description

The MAX1401 18-bit, low-power, multichannel, serial-

output ADC uses a sigma-delta modulator with a digital

decimation filter to achieve true 16-bit accuracy. The

user-selectable decimation factor of the digital filter

allows the conversion resolution to be reduced in

exchange for a higher output data rate. The device

achieves true 16-bit performance at an output data rate of

up to 480sps. In addition, the modulator sampling

frequency may be optimized for either lowest power

dissipation or highest throughput rate. The MAX1401

operates from +3V.

This device offers three fully differential input channels

that can be independently programmed with a gain

between +1V/V and +128V/V. Furthermore, it can com-

pensate an input-referred DC offset (such as system off-

set) up to 117% of the selected full-scale range. These

three differential channels may also be configured to

operate as five pseudo-differential input channels. Two

additional, fully differential system-calibration channels

are provided for gain and offset error correction. External

access is provided to the multiplexer (mux) output to

facilitate additional signal processing.

The MAX1401 can be configured to sequentially scan all

signal inputs and provide the results through the serial

interface with minimum communications overhead. When

used with a 2.4576MHz or 1.024MHz master clock, the

digital decimation filter can be programmed to produce

zeros in its frequency response at the line frequency

and associated harmonics, ensuring excellent line rejec-

tion without the need for further postfiltering.

The MAX1401 is available in a 28-pin SSOP package.

Applications

Portable Industrial Instruments

Portable Weigh Scales

Loop-Powered Systems

Pressure Transducers

Features

♦ 18-Bit Resolution, Sigma-Delta ADC

♦ 16-Bit Accuracy with No Missing Codes to 480sps

♦ Access to the Mux Output/ADC Input

♦ Low Quiescent Current

250µA (operating mode)

2µA (power-down mode)

♦ 3 Fully Differential or 5 Pseudo-Differential Signal

Input Channels

♦ 2 Additional Fully Differential Calibration

Channels/Auxiliary Input Channels

♦ Programmable Gain and Offset

♦ Fully Differential Reference Inputs

♦ Converts Continuously or On Command

♦ Automatic Channel Scanning and Continuous

Data Output Mode

♦ Operates with Analog and Digital Supplies

from +2.7V to +3.6V

♦ SPI™/QSPI™-Compatible 3-Wire Serial Interface

♦ 28-Pin SSOP Package

SCLK

DIN

DOUT

INT

DGND

AIN5

CALOFF+

CALOFF-

REFIN+

REFIN-

CALGAIN+

CALGAIN-

AIN6

AIN4

AIN3

AIN2

AIN1

V+

AGND

ADCIN-

ADCIN+

MUXOUT-

MUXOUT+

RESET

CLKOUT

CLKIN

SSOP

TOP VIEW

MAX1401

SPI and QSPI are trademarks of Motorola, Inc.

Pin Configuration

Ordering Information

28 SSOP

PIN-PACKAGETEMP RANGE

0°C to +70°C

-40°C to +85°CMAX1401EAI

MAX1401CAI

PART

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Summary of content (36 pages)

PAGE 1
9-1480; Rev 1; 7/02 KIT ATION EVALU E L B A AVAIL +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The MAX1401 is available in a 28-pin SSOP package.
PAGE 2
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ABSOLUTE MAXIMUM RATINGS Maximum Current Input into Any Pin ..................................50mA Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C) ........524mW Operating Temperature Ranges MAX1401CAI .....................................................0°C to +70°C MAX1401EAI...................................................-40°C to +85°C Storage Temperature Range ............................
PAGE 3
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OFFSET DAC Offset DAC Range (Note 8) Offset DAC Resolution Offset DAC Full-Scale Error Unipolar mode -116.7 116.7 Bipolar mode -58.35 58.35 Unipolar mode 16.7 Bipolar mode 8.
PAGE 4
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL AIN and REFIN Input Sampling Frequency fS REFIN+ - REFIN- Voltage (Note 15) CONDITIONS MIN TYP MAX (Table 15) ±5% for specified performance; functional with lower VREF UNITS Hz 1.
PAGE 5
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.
PAGE 6
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC ELECTRICAL CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER DISSIPATION (V+ = VDD = +3.3V, digital inputs = 0 or VDD, external CLKIN, burn-out currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.
PAGE 7
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1401 Note 16: These specifications apply to CLKOUT only when driving a single CMOS load. Note 17: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate correctly. Note 18: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
PAGE 8
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC TIMING CHARACTERISTICS (continued) (V+ = +2.7V to +3.6V, VDD = +2.7V to +3.6V, AGND = DGND, fCLKIN = 2.4576MHz, input logic 0 = 0V, logic 1 = VDD, TA = TMIN to TMAX, unless otherwise noted.
PAGE 9
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC DIFFERENTIAL NONLINEARITY 480sps GAIN = +1V/V 262, 144 pts 10 480sps GAIN = +1V/V 262, 144 pts 5 INL (ppm) 0 0 -5 -5 -10 -10 -15 -15 -1.0 -0.5 0 0.5 -1.0 1.0 DIFFERENTIAL INPUT VOLTAGE (V) VDD SUPPLY CURRENT vs. TEMPERATURE (20sps OUTPUT DATA RATE UNBUFFERED) 200 150 100 300 VDD = +3.6V (NOTE 30) 50 0 350 300 200 150 100 -25 0 25 50 75 100 250 200 150 100 VDD = +3.6V (NOTE 30) 50 VDD = +3.
PAGE 10
Typical Operating Characteristics (continued) (V+ = +3V, VDD = +3V, VREFIN+ = +1.25V, REFIN- = AGND, fCLKIN = 2.4576MHz, TA = +25°C, unless otherwise noted.) VDD SUPPLY CURRENT vs. TEMPERATURE (240sps OUTPUT DATA RATE UNBUFFERED) 350 300 250 200 150 100 500 400 300 200 100 VDD = +3.6V (NOTE 30) 50 MAX1401-10 600 VDD SUPPLY CURRENT (µA) 400 VDD = +3.6V (NOTE 30) 0 0 -50 -25 0 25 50 75 -50 100 -25 0 25 50 75 100 TEMPERATURE (°C) V+ SUPPLY CURRENT vs.
PAGE 11
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC PIN NAME FUNCTION 1 CLKIN Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT unconnected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1. 2 CLKOUT Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and CLKOUT.
PAGE 12
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1401 Pin Description (continued) PIN FUNCTION CALGAIN- Negative Gain Calibration Input. Used for system gain calibration. It forms the negative input of a fully differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the system.
PAGE 13
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Circuit Description The MAX1401 is a low-power, multichannel, serialoutput, sigma-delta ADC designed for applications with a wide dynamic range, such as weigh scales and pressure transducers. The functional diagram in Figure 2 contains a switching network, a modulator, a PGA, two buffers, an oscillator, an on-chip digital filter, and a bidirectional serial communications port.
PAGE 14
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Serial Digital Interface The serial digital interface provides access to eight onchip registers (Figure 3). All serial-interface commands begin with a write to the communications register (COMM). On power-up, system reset, or interface reset, the part expects a write to its communications register. The COMM register access begins with a 0 start bit.
PAGE 15
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Data-Ready Signal (DRDY bit true or INT = low) The data-ready signal indicates that new data may be read from the 24-bit data register. After the end of a successful data register read, the data-ready signal becomes false. If a new measurement completes before the data is read, the data-ready signal becomes false. The data-ready signal becomes true again when new data is available in the data register.
PAGE 16
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC FSYNC: (Default = 0) Filter Sync Bit. When FSYNC = 0, conversions are automatically performed at a data rate determined by CLK, FS1, FS0, MF1, and MF0 bits. When FSYNC = 1, the digital filter and analog modulator are held in reset, inhibiting normal self-timed operation. This bit may be used to convert on command to minimize the settling time to valid output data, or to synchronize operation of a number of MAX1401s.
PAGE 17
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC AIN3/AIN4, and AIN5/AIN6. The available input channels for each mode are tabulated in Table 5. Note that DIFF also affects the scanning sequence when the part is placed in SCAN mode (Table 4). BOUT: (Default = 0) Burn-out Current Bit. Setting BOUT = 1 connects 100nA current sources to the selected analog input channel. This mode is used to check that a transducer has not burned out or opened circuit.
PAGE 18
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 4.
PAGE 19
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC mapped to the correct output range. Note that U/B must be set before a conversion is performed; it will not affect any data already held in the output register. CALGAIN and CALOFF When not in scan mode (SCAN = 0), A1 and A0 select which transfer function applies to CALGAIN and CALOFF. In scan mode (SCAN = 1), CALGAIN and CALOFF are always mapped to transfer-function register 3.
PAGE 20
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 8.
PAGE 21
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC CHANNEL TRANSFERFUNCTION REGISTER SCAN DIFF A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 X X AIN1–AIN6 1 1 0 X X AIN2–AIN6 1 1 0 X X AIN3–AIN6 2 1 0 X X AIN4–AIN6 2 1 0 X X AIN5–AIN6 3 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 X X X X X X X 1 X X X X X X X 1 CALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINCALGAIN+–CALGAINDo Not Us
PAGE 22
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 11. Channel ID Tag Codes CID2 CID1 CID0 CHANNEL 0 0 0 AIN1–AIN6 0 0 1 AIN2–AIN6 0 1 0 AIN3–AIN6 0 1 1 AIN4–AIN6 1 0 0 AIN1–AIN2 1 0 1 AIN3–AIN4 1 1 0 AIN5–AIN6 1 1 1 Calibration Switching Network A switching network provides selection between three fully differential input channels or five pseudo-differential channels, using AIN6 as a shared common.
PAGE 23
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC REXT RMUX CEXT Dynamic Input Impedance at the Channel Selection Network When used in unbuffered mode (BUFF = 0), the analog inputs present a dynamic load to the driving circuitry. The size of the sampling capacitor and the input sampling frequency (Figure 5) determine the dynamic load seen by the driving circuitry. The MAX1401 samples at a constant rate for all gain settings.
PAGE 24
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 13c. REXT, CEXT Values for Less than 16-Bit Gain Error in Unbuffered (BUFF = 0) Mode; 4x Modulator Sampling Frequency (MF1, MF0 = 10 ); X2CLK = 0; fCLKIN = 2.4576MHz EXTERNAL RESISTANCE, REXT (kΩ) PGA GAIN CEXT = 0pF CEXT = 50pF CEXT = 100pF CEXT = 500pF CEXT = 1000pF CEXT = 5000pF 1 7.0 3.4 2.3 0.71 0.40 0.11 2 7.0 3.4 2.3 0.71 0.40 0.11 4 5.5 3.0 2.1 0.66 0.38 0.10 8, 16, 32, 64, 128 3.8 2.
PAGE 25
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC PGA GAIN EXTERNAL RESISTANCE, REXT (kΩ) CEXT = 0pF CEXT = 50pF CEXT = 100pF CEXT = 500pF CEXT = 1000pF CEXT = 5000pF 1 10 10 10 10 10 10 2 10 10 10 10 10 10 4 10 10 10 10 10 10 8 10 10 10 10 10 10 16 10 10 10 10 10 10 32 10 10 10 10 10 10 64 10 10 10 10 10 10 128 10 10 10 10 10 10 Reference Input PGA The MAX1401 is optimized for ratiometric measurements and includes a fully
PAGE 26
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Table 15. Modulator Operating Frequency, Sampling Frequency, and 16-Bit Data Output Rates CLKIN FREQUENCY, fCLKIN (MHz) MODULATOR FREQUENCY, fM (kHz) AVAILABLE OUTPUT DATA RATES AT 16-BIT ACCURACY (sps) 20, 25 CLK MF1 MF0 AIN/REFIN SAMPLING FREQUENCY, fS (kHz) 2.048 0 0 0 16 8 1.024 2.048 0 0 1 32 16 40, 50 1.024 2.048 0 1 0 64 32 80, 100 1.024 2.048 0 1 1 128 64 160, 200 2.4576 4.
PAGE 27
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC OUTPUT DATA RATE (sps) -3dB FREQ. (Hz) 50 13.1 x1 5.72 x2 3.21 x4 2.10 x8 1.41 x16 1.42 x32 1.44 x64 1.38 x128 1.34 MF1:MF0 = 0 FS1:FS0 = 0 TYPICAL OUTPUT NOISE (µVRMS) FOR VARIOUS PROGRAMMABLE GAINS BIT STATUS 60 15.7 6.29 3.57 2.30 1.55 1.61 1.56 1.49 1.56 FS1:FS0 = 1 300 78.6 80.6 39.8 19.3 10.2 6.14 4.25 3.03 3.52 FS1:FS0 = 2 600 157.2 436 225 116 57.1 28.8 15.0 8.70 5.
PAGE 28
Offset-Correction DAC The MAX1401 provides a coarse (3-bit plus sign) offset correction DAC at the modulator input. Use this DAC to remove the offset component in the input signal, allowing the ADC to operate on a more sensitive range. The DAC offsets up to ±116.7% of the selected range in ±16.7% increments for unipolar mode and up to ±58.3% of the selected range in ±8.3% increments for bipolar mode.
PAGE 29
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC The SINC1 function results in a faster settling response while retaining the same frequency response notches as the default SINC3 filter. This allows the filter to settle faster at the expense of resolution and quantization noise. The SINC1 filter settles in one data word period. With 60Hz notches (60Hz data rate), the settling time would be 1 / 60Hz or 16.7ms, whereas the SINC3 filter would settle in 3 / 60Hz or 50ms.
PAGE 30
input can be up to four-times the output data period. For a synchronized step input (using the FSYNC function or the internal scanning logic), the settling time is three-times the output data period. resistance will cause an offset error of less than 10µV). Therefore, where any significant source impedances are required, Maxim recommends operating the part in buffered mode.
PAGE 31
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC MAX1401 /* Assumptions: ** The MAX140X's CS pin is tied to ground ** The MAX140X's INT pin drives a falling-edge-triggered interrupt ** MAX140X's DIN is driven by MOSI, DOUT drives MISO, and SCLK drives SCLK */ /* Low-level function to write 8 bits using 68HC11 SPI */ void WriteByte (BYTE x) { /* System-dependent: write to SPI hardware and wait until it is finished */ HC11_SPDR = x; while (HC11_SPSR & HC11_SPSR_SPIF) { /* idle loop */ } }
PAGE 32
MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Bit-Banging Interface (80C51, PIC16C54) VDD RESET 8051 P3.0 DOUT DIN P3.1 SCLK CS MAX1401 Any microcontroller can use general-purpose I/O pins to interface to the MAX1401. If a bidirectional or opendrain I/O pin is available, reduce the interface pin count by connecting DIN to DOUT (Figure 13). Listing 2 shows how to emulate the SPI in software. Use the same initialization routine shown in Listing 1.
PAGE 33
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Temperature Measurement Figure 15 shows a connection from a thermocouple to the MAX1401. In this application, the MAX1401 is operated in its buffered mode to allow large decoupling capacitors on the front end. These decoupling capacitors eliminate any noise pickup from the thermocouple leads. When the MAX1401 is operated in buffered mode, it has a reduced common-mode range.
PAGE 34
Loop-Powered, 4–20mA Transmitters Low power, single-supply operation, and easy interfacing with optocouplers make the MAX1401 ideal for loop-powered 4–20mA transmitters. Loop-powered transmitters draw their power from the 4–20mA loop, limiting the transmitter circuitry to a current budget of 4mA. Tolerances in the loop further limit this current budget to 3.5mA. Since the MAX1401 consumes only 250µA, a total of 3.25mA remains to power the remaining transmitter circuitry.
PAGE 35
+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC Design the printed circuit board so the analog and digital sections are separated and confined to different areas of the board. Join the digital and analog ground planes at only one point. If the MAX1401 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the MAX1401.
PAGE 36
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 2 SSOP.EPS MAX1401 +3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C D 0.20 0.09 0.004 0.008 SEE VARIATIONS E 0.205 e 0.212 0.0256 BSC 5.