Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 48

General Description

The MAX1421 is a 3.3V, 12-bit analog-to-digital con-

verter (ADC), featuring a fully-differential input,

pipelined, 12-stage ADC architecture with wideband

track-and-hold (T/H) and digital error correction incor-

porating a fully-differential signal path. The MAX1421 is

optimized for low-power, high-dynamic performance

applications in imaging and digital communications.

The converter operates from a single 3.3V supply, con-

suming only 188mW while delivering a typical signal-to-

noise ratio (SNR) of 66dB at an input frequency of

15MHz and a sampling frequency of 40Msps. The fully-

differential input stage has a small signal -3dB band-

width of 400MHz and may be operated with

single-ended inputs.

An internal 2.048V precision bandgap reference sets

the full-scale range of the ADC. A flexible reference

structure accommodates an internal or externally

applied buffered or unbuffered reference for applica-

tions requiring increased accuracy or a different input

voltage range.

In addition to low operating power, the MAX1421 fea-

tures two power-down modes, a reference power-down

and a shutdown mode. In reference power-down, the

internal bandgap reference is deactivated, resulting in

a typical 2mA supply current reduction. For idle peri-

ods, a full shutdown mode is available to maximize

power savings.

The MAX1421 provides parallel, offset binary, CMOS-

compatible three-state outputs.

The MAX1421 is available in a 7mm x 7mm, 48-pin

TQFP package, and is specified over the commercial

(0°C to +70°C) and the extended industrial (-40°C to

+85°C) temperature ranges.

Pin-compatible higher- and lower-speed versions of the

MAX1421 are also available. Please refer to the

MAX1420 data sheet for a frequency of 60Msps and

the MAX1422 data sheet for a frequency of 20Msps.

________________________Applications

Medical Ultrasound Imaging

CCD Pixel Processing

Data Acquisition

Radar

IF and Baseband Digitization

Features

♦ Single 3.3V Power Supply

♦ 67dB SNR at f

= 5MHz

♦ 66dB SNR at f

= 15MHz

♦ Internal, 2.048V Precision Bandgap Reference

♦ Differential, Wideband Input T/H Amplifier

♦ Power-Down Modes

180mW (Reference Shutdown Mode)

10µW (Shutdown Mode)

♦ Space-Saving 48-Pin TQFP Package

MAX1421

12-Bit, 40Msps, 3.3V, Low-Power ADC

with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

DGND

AGND

INP

INN

AGND

48-TQFP

MAX1421

AGND

CLK

AGND

DGND

AGND

CML

REFN

REFP

REFIN

AGND

D11

D10

Pin Configuration

19-1900; Rev 1; 5/06

Ordering Information

Functional Diagram appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+Denotes lead-free package.

PART* TEMP RANGE

PIN-

PACKAGE

PKG

CODE

M AX1421CCM

0°C to +70°C 48 TQFP

C48-2

M AX1421ECM

-40°C to +85°C 48 TQFP

C48-2

M AX1421ECM+

-40°C to +85°C 48 TQFP

C48-2

Summary of content (17 pages)

PAGE 1
9-1900; Rev 1; 5/06 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference Ordering Information PART* TEMP RANGE Functional Diagram appears at end of data sheet. PINPACKAGE PKG CODE MAX1421CCM 0°C to +70°C 48 TQFP C48-2 MAX1421ECM -40°C to +85°C 48 TQFP C48-2 MAX1421ECM+ -40°C to +85°C 48 TQFP C48-2 +Denotes lead-free package.
PAGE 2
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS AVDD, DVDD to AGND ..............................................-0.3V to +4V DVDD, AVDD to DGND..............................................-0.3V to +4V DGND to AGND.....................................................-0.3V to +0.3V INP, INN, REFP, REFN, REFIN, CML, CLK, CLK,....................(AGND - 0.3V) to (AVDD + 0.3V) D0–D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.
PAGE 3
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference (V AVDD = V DVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA ≥ +25°C guaranteed by production test, TA < +25°C guarnateed by design and characterization. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Gain DG ±1 % Differential Phase DP ±0.25 degrees 32.
PAGE 4
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (V AVDD = V DVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA ≥ +25°C guaranteed by production test, TA < +25°C guarnateed by design and characterization. Typical values are at TA = +25°C.
PAGE 5
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference (V AVDD = V DVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference, fCLK = 40MHz (50% duty cycle), digital output load CL ≈ 10pF, TA ≥ +25°C guaranteed by production test, TA < +25°C guarnateed by design and characterization. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 7
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference fIN = 5.52MHz 68 66 64 68 62 64 60 85 -80 -40 -15 TEMPERATURE (°C) fIN = 5.52MHz 60 64 62 60 -15 10 35 -15 INTEGRAL NONLINEARITY NONLINEARITY vs.INTEGRAL DIGITAL OUTPUT CODE vs. DIGITAL OUTPUT CODE 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0 0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.00 60 35 60 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.500 0.375 0.125 0 -0.125 -0.250 -0.
PAGE 8
Typical Operating Characteristics (continued) (VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE SNR/SINAD, -THD/SFDR vs. CLOCK FREQUENCY SFDR 75 2.0750 70 MAX1421 toc23 -THD MAX1421 toc22 2.0625 65 SNR 60 VREFIN (V) SNR/SINAD, -THD/SFDR (dB, dBc) 80 SINAD 2.
PAGE 9
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference PIN NAME FUNCTION 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 AGND Analog Ground. Connect all return paths for analog signals to AGND. 2, 3, 10, 11, 14, 15, 20, 42, 47 AVDD Analog Supply Voltage. For optimum performance bypass each pin to the closest AGND with a parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between AVDD and AGND.
PAGE 10
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference Detailed Description The MAX1421 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every halfclock-cycle. Including the delay through the output latch, the latency is seven clock cycles. A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code.
PAGE 11
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference MAX1421 AVDD 50Ω (AV2DD) CML R 0.22µF 1nF AVDD 2 50Ω R REFP MAX4284 R R AVDD 2 0.22µF (AV2DD + 1V) 1nF MAX1421 AVDD 4 R 50Ω R ( ) REFN AVDD + 1V 2 MAX4284 0.22µF 1nF R AVDD 4 REFIN R AGND +1V Figure 3.
PAGE 12
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference OE INP D11–D0 ADC INN tBD tBE AVDD OUTPUT DATA D11–D0 10kΩ HIGH-Z VALID DATA 10kΩ Figure 5. Output Enable Timing CLK 10kΩ 10kΩ CLK MAX1421 AGND Figure 4. Simplified Clock Input Circuit Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1421 clock input.
PAGE 13
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference MAX1421 7 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLK tDO tCH tCL CLK DATA OUTPUT N-7 N-6 N-5 N-4 N-3 N-2 N-1 N Figure 6. System and Output Timing Diagram Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1421 for optimum performance.
PAGE 14
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference +5V 0.1µF LOWPASS FILTER INP MAX4108 RISO 50Ω 0.1µF 300Ω CIN* 22pF 0.1µF -5V MAX1421 600Ω 0.1µF 44pF* 600Ω 300Ω CML 0.1µF 0.22µF +5V 1nF +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INN MAX4108 RISO 50Ω 300Ω -5V CIN* 22pF 0.1µF 300Ω 300Ω 300Ω *TWO CIN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROVE PERFORMANCE. Figure 7.
PAGE 15
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference MAX1421 25Ω INP 22pF * 0.1µF 1 VIN T1 2 N.C. 3 MAX1421 44pF * 6 5 4 CML 0.22µF 1nF MINICIRCUITS T1–1T–KK81 25Ω INN 22pF * *REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE. Figure 8. Using a Transformer for AC-Coupling VIN RISO 50Ω 0.1µF MAX4108 100Ω 1kΩ CIN 22pF 0.22µF 1nF INP MAX1421 CML RISO 50Ω INN 100Ω CIN 22pF Figure 9.
PAGE 16
MAX1421 12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 × log10      (V 2 2 2 2 + V3 + V4 + V5 V1 2 )      where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
PAGE 17
12-Bit, 40Msps, 3.3V, Low-Power ADC with Internal Reference 32L/48L,TQFP.EPS PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm 21-0054 F 1 2 PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm 21-0054 F 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.