Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 28

General Description

The MAX1426 10-bit, monolithic analog-to-digital con-

verter (ADC) is capable of a 10Msps sampling rate. This

device features an internal track-and-hold (T/H) amplifier

for excellent dynamic performance; at the same time, it

minimizes the number of external components. Low

input capacitance of only 8pF minimizes input drive

requirements. A wide input bandwidth (up to 150MHz)

makes this device suitable for digital RF/IF downconvert-

er applications employing undersampling techniques.

The MAX1426 employs a differential pipelined architec-

ture with a wideband T/H amplifier to maximize through-

put while limiting power consumption to only 156mW.

The MAX1426 generates an internal +2.5V reference

that supplies three additional reference voltages

(+3.25V, +2.25V, and +1.25V). These reference volt-

ages provide a differential input range of +2V to -2V.

The analog inputs are biased internally to correct the

DC level, eliminating the need for external biasing on

AC-coupled applications.

A separate +3V digital logic supply input allows for

separation of digital and analog circuitry. The output

data is in two’s complement format. The MAX1426 is

available in the space-saving 28-pin SSOP package.

For a pin-compatible version at a higher data rate, refer

to the MAX1424 or MAX1425

Applications

Medical Ultrasound Imaging

CCD Pixel Processing

IR Focal Plane Array

Radar

IF and Baseband Digitization

Set-Top Boxes

Features

o Differential Inputs for High Common-Mode

Noise Rejection

o 61dB Signal-to-Noise Ratio (at f

= 2MHz)

o Internal +2.5V Reference

o 150MHz Input Bandwidth

o Wide ±2V Input Range

o Low Power Consumption: 156mW

o Separate Digital Supply Input for 3V Logic

Compatibility

o Single +5V Operation Possible

MAX1426

10-Bit, 10Msps ADC

________________________________________________________________

Maxim Integrated Products

DGND

OE/PD

CLK

CMLN

CMLP

INN

INP

AGND

CML

REFN

REFIN

REFP

AGND

SSOP

TOP VIEW

MAX1426

CLK

INP

INTERFACE

PIPELINE ADC

REF SYSTEM +

BIAS

OUTPUT

DRIVERS

REF

REFIN REFP CML REFN OE/PD

AGND

DGND

D9–D0

INN

T/H

MAX1426

Functional Diagram

19-1598 Rev 1; 7/11

PART

MAX1426CAI+

MAX1426EAI+ -40°C to +85°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

28 SSOP

Pin Configuration

Ordering Information

Denotes a lead(Pb)-free/RoHS-compliant package.

Devices are also available in a tape-and-reel package.

Specify tape and reel by adding “T” to the number when order-

ing.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Summary of content (16 pages)

PAGE 1
9-1598 Rev 1; 7/11 10-Bit, 10Msps ADC The MAX1426 10-bit, monolithic analog-to-digital converter (ADC) is capable of a 10Msps sampling rate. This device features an internal track-and-hold (T/H) amplifier for excellent dynamic performance; at the same time, it minimizes the number of external components. Low input capacitance of only 8pF minimizes input drive requirements.
PAGE 2
MAX1426 10-Bit, 10Msps ADC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ........................................................ -0.3V to +6V DVDD to DGND ....................................................... -0.3V to +6V AVDD to DGND ........................................................ -0.3V to +6V DGND to AGND ................................................................. ±0.3V REFP, REFIN, REFN, CMLN, CMLP, CML, INP, INN .....................(VAGND - 0.3V) to (VAVDD + 0.3V) CLK, OE/PD, D0–D9 .........
PAGE 3
10-Bit, 10Msps ADC (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Effective Number of Bits SYMBOL ENOB CONDITIONS f = 2MHz IMD f1 = 1.98MHz, f2 = 2.00MHz (-7dB FS, each tone) (Note 5) Input Resistance RIN Either input to ground Input Capacitance CIN Either input to ground Intermodulation Distortion MIN TYP 9.
PAGE 4
MAX1426 10-Bit, 10Msps ADC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE OUTPUT (REFP, CML, REFN; internal +2.5V reference) Positive Reference VREFP (Note 1) 3.25 V Common-Mode Reference Voltage VCML (Note 1) 2.
PAGE 5
10-Bit, 10Msps ADC (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output loading 35pF, fCLK = 10MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS Conversion Rate CONV Clock Frequency fCLK 0.
PAGE 6
Typical Operating Characteristics (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.) fINP = 2MHz 0.4 0.4 -1.0 -2.0 0.2 0 -0.2 -0.4 AMPLITUDE (dB) 0.2 DNL (LSB) 0 -0.2 -0.6 -4.0 -5.0 -6.0 -0.8 -0.4 -7.0 -1.0 -0.6 -1.2 200 400 600 800 200 400 600 800 1000 0.01 0.
PAGE 7
10-Bit, 10Msps ADC 40 THD (dB) THD (dB) -40 -45 -30 -15 -60 0 -45 -30 -15 -60 0 -30 -15 INPUT (dB) INPUT (dB) EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 1.997MHz) EFFECTIVE NUMBER OF BITS vs. POWER (fIN = 4.942MHz) EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY 8 4 9.6 6 ENOB (bits) ENOB (bits) 8 6 10.0 4 2 2 -45 -30 15 -60 0 9.2 8.8 8.4 0 0 -45 -30 15 8.0 0 2 3 4 INPUT (dB) INPUT (dB) INPUT FREQUENCY (MHz) SIGNAL-TO-NOISE RATIO vs.
PAGE 8
Typical Operating Characteristics (continued) (VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 10MHz (50% duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.) FFT PLOT (fIN = 2MHz) FFT PLOT (fIN = 5MHz) -20 MAGNITUDE (dB) -40 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 3 4 5 6 7 8 9 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.18 0.80 2.
PAGE 9
10-Bit, 10Msps ADC PIN NAME FUNCTION 1, 7 AGND Analog Ground. Connect all return paths for analog signals to these pins. 2, 8 AVDD Analog Supply Voltage Input. Bypass with a parallel combination of 2.2µF, 0.1µF, and 100pF capacitors to AGND. Bypass each supply input to the closest AGND (e.g., capacitors between pins 1 and 2). 3 REFP Positive Reference Output. Bypass to AGND with a 0.1µF capacitor. If the internal reference is disabled, REFP can accept an external voltage.
PAGE 10
MAX1426 10-Bit, 10Msps ADC Detailed Description the residue by two and the next stage in the pipeline performs a similar operation. The MAX1426 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half clock cycle. Counting the delay through the output latch, there is a 5.5 clock-cycle latency. A 2-bit flash ADC converts the input voltage to digital code.
PAGE 11
10-Bit, 10Msps ADC MAX1426 5.5 CLOCK-CYCLE LATENCY n n+1 n+2 n+3 n+4 n+5 n+6 n+7 ANALOG INPUT CLOCK INPUT n-6 DATA OUTPUT n-5 n-4 n-3 n-2 n-1 n n+1 Figure 3. System Timing Diagram Table 1. MAX1426 Output Code tCLK DIFFERENTIAL INPUT tCI tCH INPUT CLK tOD OUTPUT DATA DATA 0 DATA 1 DATA 2 Figure 4. Output Timing Diagram and REFN. In this mode, the voltages at these pins are set to their nominal values (see Electrical Characteristics).
PAGE 12
MAX1426 10-Bit, 10Msps ADC heavy loads, as they are specified to deliver only 200µA for TTL compatibility. If an application needs output buffering, use 74LS74s or 74ALS541s as required. high-speed op amps. In this application, the amplifier outputs are directly coupled to the inputs. This configuration can also be modified for AC-coupled applications. The MAX1426 includes a DC level-shifting circuit internal to the part, allowing for AC-coupled applications.
PAGE 13
10-Bit, 10Msps ADC A small transformer (Figure 8) provides isolation and AC-coupling to the ADC’s input. Connecting the transformer's center tap to CML provides a +2.25VDC level shift to the input. Transformer coupling reduces the need for high-speed op amps, thereby reducing cost. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements.
PAGE 14
MAX1426 10-Bit, 10Msps ADC R4 25Ω INN VIN ±V ±2V 0.1µF 50Ω INP 50Ω MAX4108 C3 22pF 22pF 100Ω MAX1426 1 IN1 N.C. 2 R2 100Ω R3 100Ω 3 T1 MAX1426 6 5 4 MINICIRCUITS KKB1 CML 100Ω INN 0.1µF 0.1µF R5 25Ω INP C9 22pF Figure 9. Single-Ended AC-Coupled Input Signal Figure 8. Using a Transformer for AC-Coupling Bypassing and Board Layout The MAX1426 requires high-speed board layout design techniques.
PAGE 15
10-Bit, 10Msps ADC For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 16
MAX1426 10-Bit, 10Msps ADC Revision History REVISION NUMBER REVISION DATE 0 1/00 Initial release 1 7/11 Updated Ordering Information, Absolute Maximum Ratings, Electrical Characteristics, and Package Information DESCRIPTION PAGES CHANGED — 1, 2, 15 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.