Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 32

General Description

The MAX1444 10-bit, 3V analog-to-digital converter

(ADC) features a pipelined 10-stage ADC architecture

with fully differential wideband track-and-hold (T/H)

input and digital error correction incorporating a fully

differential signal path. This ADC is optimized for low-

power, high dynamic performance applications in

imaging and digital communications. The MAX1444

operates from a single 2.7V to 3.6V supply, consuming

only 57mW while delivering a 59.5dB signal-to-noise

ratio (SNR) at a 20MHz input frequency. The fully differ-

ential input stage has a 400MHz -3dB bandwidth and

may be operated with single-ended inputs. In addition

to low operating power, the MAX1444 features a 5µA

power-down mode for idle periods.

An internal 2.048V precision bandgap reference is

used to set the ADC full-scale range. A flexible refer-

ence structure allows the user to supply a buffered,

direct, or externally derived reference for applications

requiring increased accuracy or a different input volt-

age range.

Higher speed, pin-compatible versions of the MAX1444

are also available. Please refer to the MAX1446 data

sheet (60Msps) and the MAX1448 data sheet

(80Msps).

The MAX1444 has parallel, offset binary, CMOS-com-

patible three-state outputs that can be operated from

1.7V to 3.6V to allow flexible interfacing. The device is

available in a 5x5mm 32-pin TQFP package and is

specified over the extended industrial (-40°C to +85°C)

temperature range.

________________________Applications

Ultrasound Imaging

CCD Imaging

Baseband and IF Digitization

Digital Set-Top Boxes

Video Digitizing Applications

Features

o Single 3.0V Operation

o Excellent Dynamic Performance

59.5dB SNR at f

= 20MHz

74dBc SFDR at f

= 20MHz

o Low Power

19mA (Normal Operation)

5μA (Shutdown Mode)

o Fully Differential Analog Input

o Wide 2V

p-p Differential Input Voltage Range

o 400MHz -3dB Input Bandwidth

o On-Chip 2.048V Precision Bandgap Reference

o CMOS-Compatible Three-State Outputs

o 32-Pin TQFP Package

o Evaluation Kit Available

MAX1444

10-Bit, 40Msps, 3.0V, Low-Power

ADC with Internal Reference

________________________________________________________________

Maxim Integrated Products

MAX1444

TQFP

TOP VIEW

32 28

293031

REFIN

GND

REFOUT

REFP

1611 12

GND

CLK

GND

OGND

24 D4

T.P.

8GND

IN-

IN+

GND

COM

REFN

Pin Configuration

19-1745; Rev 3; 8/10

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

Functional Diagram appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1444EHJ -40°C to +85°C 32 TQFP

MAX1444EHJ/V+ -40°C to +85°C 32 TQFP

/V Denotes an automotive qualified part.

Denotes a lead(Pb)-free/RoHS-compliant package.

Summary of content (20 pages)

PAGE 1
9-1745; Rev 3; 8/10 KIT ATION EVALU LE B A IL A AV 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1444 10-bit, 3V analog-to-digital converter (ADC) features a pipelined 10-stage ADC architecture with fully differential wideband track-and-hold (T/H) input and digital error correction incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1444 operates from a single 2.
PAGE 2
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.
PAGE 3
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.
PAGE 4
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3V; OVDD = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V; REFOUT connected to REFIN through a 10kΩ resistor; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 40MHz; TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.
PAGE 7
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference 61 -50 61 60 SINGLE ENDED DIFFERENTIAL 58 57 SINAD (dB) -55 59 THD (dBc) -60 56 DIFFERENTIAL SINGLE ENDED 45 -75 1 10 100 1 10 1 100 10 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER 65 MAX1444-13 fIN = 19.91MHz fIN = 19.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dB FS, fCLK = 40MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE fIN = 19.91MHz fIN = 19.91MHz 0.4 MAX1444-21 70 MAX1444-19 -60 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) MAX1444-20 TOTAL HARMONIC DISTORTION vs. TEMPERATURE 0.3 66 -64 -72 62 58 0 -0.1 -0.2 54 -76 0.
PAGE 9
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ANALOG POWER-DOWN CURRENT vs. ANALOG POWER SUPPLY fIN = 7.51MHz OE = OVDD, PD = VDD 4.5 4 10 MAX1444-30 5.0 MAX1444-28 5 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY MAX1444-29 DIGITAL SUPPLY CURRENT vs. TEMPERATURE PD = VDD, OE = OVDD 8 IOVDD (μA) IVDD (μA) IOVDD (mA) 4.0 3 3.5 2 6 4 3.0 1 2.0 0 -40 -15 10 35 60 0 2.70 85 2.85 3.00 3.15 3.30 3.45 3.60 1.2 1.8 2.4 3.
PAGE 10
-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 Pin Description PIN NAME FUNCTION 1 REFN Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1μF capacitor. 2 COM Common-Mode Voltage Output. Bypass to GND with a >0.1μF capacitor. 3, 9, 10 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2μF in parallel with 0.1μF. 4, 5, 8, 11, 14, 30 GND Analog Ground 6 IN+ Positive Analog Input.
PAGE 11
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1444 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code.
PAGE 12
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1444 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be connected to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range.
PAGE 13
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference -60 fIN = 13.24MHz AT-0.5dB FS 85 MAX1444 90 fIN = 13.24MHz AT-0.5dB FS -64 THD (dBc) SFDR (dBc) 80 75 -68 -72 70 -76 65 60 -80 20 30 40 50 60 70 20 30 CLOCK DUTY CYCLE (%) Figure 3a. Spurious-Free Dynamic Range vs. Clock Duty Cycle (Differential Input) 61 50 60 70 Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle (Differential Input) 61 fIN = 13.24MHz AT-0.5dB FS 60 fIN = 13.24MHz AT-0.
PAGE 14
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference System Timing Requirements Using Transformer Coupling Figure 6 shows the relationship between the clock input, analog input, and data output. The MAX1444 samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 5 shows the relationship between the input clock parameters and the valid output data.
PAGE 15
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 5V 0.1μF LOWPASS FILTER IN+ MAX4108 RISO 50Ω 0.1μF 300Ω CIN 22pF 0.1μF -5V MAX1444 600Ω 300Ω 600Ω COM 5V 0.1μF 5V 0.1μF 600Ω INPUT 0.1μF LOWPASS FILTER MAX4108 300Ω 0.1μF -5V IN- MAX4108 RISO 50Ω CIN 22pF 300Ω -5V 0.1μF 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion REFP 25Ω IN+ 10pF 0.1μF VIN 3 N.C. 5 1 T1 VIN 0.
PAGE 16
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference 3.3V 0.1μF 3.3V N.C. 0.1μF 2.048V 1 MAX6062 31 0.1μF 2 16.2kΩ 3 32 1 5 162Ω 1μF 4 3 MAX4250 2 10Hz LOWPASS FILTER 29 2 1 100μF 0.1μF 0.1μF REFOUT REFIN REFP MAX1444 N=1 REFN COM 0.1μF 10Hz LOWPASS FILTER 0.1μF N.C. 29 31 32 1 0.1μF 2 0.1μF 0.1μF 2.2μF 10V REFOUT REFIN REFP MAX1444 N = 1000 REFN COM 0.1μF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. Figure 10.
PAGE 17
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference MAX1444 3.3V 0.1μF N.C. 29 31 REFOUT REFIN 1 2.0V 2 32 3.3V 21.5kΩ 3 MAX6066 4 1 1 47Ω 1/4 MAX4252 2 2 21.5kΩ 3 REFP MAX1444 2.0V AT 8mA 11 10μF 6V 330μF 6V 0.1μF 0.1μF N=1 REFN COM 0.1μF 1.47kΩ 1μF 1.5V 3.3V 5 3.3V 1.5V AT 0mA 4 7 47Ω 1/4 MAX4252 0.1μF 6 11 21.5kΩ MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 10μF 6V 330μF 6V 1.47kΩ 1.0V 3.3V 10 1.
PAGE 18
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference power-supply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended.
PAGE 19
10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: (SINAD − 1.76) ENOB = 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the input signal’s first four harmonics to the fundamental itself.
PAGE 20
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference Revision History REVISION NUMBER REVISION DATE 3 8/10 DESCRIPTION Added MAX1444EHJ/V+ to Ordering Information PAGES CHANGED 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.