Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 32

General Description

The MAX1446 10-bit, 3V analog-to-digital converter

(ADC) features a fully differential input, a pipelined 10-

stage ADC architecture with digital error correction and

wideband track and hold (T/H) incorporating a fully dif-

ferential signal path. This ADC is optimized for low-

power, high dynamic performance applications in

imaging and digital communications. The MAX1446

operates from a single 2.7V to 3.6V supply, consuming

only 90mW while delivering a 59.5dB signal-to-noise

ratio (SNR) at a 20MHz input frequency. The fully differ-

ential input stage has a 400MHz, -3dB bandwidth and

may be operated with single-ended inputs. In addition

to low operating power, the MAX1446 features a 5µA

power-down mode for idle periods.

An internal 2.048V precision bandgap reference is used

to set the ADC full-scale range. A flexible reference

structure allows the user to supply a buffered, direct or

externally derived reference for applications requiring

increased accuracy or a different input voltage range.

Lower and higher speed, pin-compatible versions of

the MAX1446 are also available. Refer to the MAX1444

data sheet for a 40Msps version, the MAX1448 data

sheet for an 80Msps version, and the MAX1449 data

sheet for a 105Msps version.

The MAX1446 has parallel, offset binary, three-state

outputs that can be operated from 1.7V to 3.3V to allow

flexible interfacing. The device is available in a 5mm x

5mm, 32-pin TQFP package and is specified over the

extended industrial (-40°C to +85°C) and automotive

(-40°C to +105°C) temperature ranges.

________________________Applications

Ultrasound Imaging

CCD Imaging

Baseband and IF Digitization

Digital Set-Top Boxes

Video Digitizing Applications

Features

o Single 3.0V Operation

o Excellent Dynamic Performance

59.5dB SNR at f

= 20MHz

73dB SFDR at f

= 20MHz

o Low Power:

30mA (Normal Operation)

5µA (Shutdown Mode)

o Fully Differential Analog Input

o Wide 2V

P-P

Differential Input Voltage Range

o 400MHz -3dB Input Bandwidth

o On-Chip 2.048V Precision Bandgap Reference

o CMOS-Compatible Three-State Outputs

o 32-Pin TQFP Package

o Evaluation Kit Available (MAX1448 EV Kit)

MAX1446

10-Bit, 60Msps, 3.0V, Low-Power

ADC with Internal Reference

________________________________________________________________

Maxim Integrated Products

CLK

IN+

CONTROL

PIPELINE ADC

REF SYSTEM +

BIAS

OUTPUT

DRIVERS

REF

REFINREFOUT REFP COM REFN OE

GND

OGND

D9–D0

IN-

T/H

MAX1446

Functional Diagram

19-1729; Rev 4; 11/08

EVALUATION KIT

AVAILABLE

Ordering Information

PART TEMP RANGE

PIN-

PACKAGE

MAX1446EHJ+ -40°C to +85°C 32 TQFP

MAX1446GHJ+ -40°C to +105°C 32 TQFP

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Pin-Compatible,

Lower/Higher Speed Versions

PART SAMPLING SPEED (Msps)

MAX1444 40

MAX1448 80

MAX1449 105

Denotes a lead(Pb)-free/RoHS-compliant package.

Summary of content (20 pages)

PAGE 1
9-1729; Rev 4; 11/08 KIT ATION EVALU E L B A AVAIL 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1446 10-bit, 3V analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in imaging and digital communications. The MAX1446 operates from a single 2.
PAGE 2
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND.........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.
PAGE 3
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 4
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
PAGE 5
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) HD2 -70 -50 HD3 HD2 -40 -50 -60 -80 -80 -80 -90 -90 -90 -100 -100 -100 10 15 20 25 30 35 5 10 15 20 25 30 0 35 20 25 30 FFT PLOT (fIN = 50MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) HD3 -60 SFDR = 70dBc SNR = 59.1dB THD = -67.1dBc SINAD = 58.
PAGE 7
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference SIGNAL-TO-NOISE AND DISTORTION vs. ANALOG INPUT FREQUENCY (AIN = -0.5dBFS) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY (AIN = -0.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE AND DISTORTION vs. TEMPERATURE 66 SINAD (dB) -68 fIN = 19.943MHz, AIN = -0.5dBFS -72 TA = +105°C -76 fIN = 7.5MHz 0.4 0.3 62 0.2 INL (LSB) -64 0.5 MAX1446 toc20 fIN = 19.943MHz, AIN = -0.5dBFS THD (dBc) 70 MAX1446 toc19 -60 INTEGRAL NONLINEARITY vs.
PAGE 9
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference (VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) 4.5 4.0 IVDD (μA) IOVDD (mA) TA = +105°C 12 8 10 3.5 MAX1446 toc30 16 OE = OVDD, PD = VDD PD = VDD, OE = OVDD 8 IOVDD (μA) fIN = 7.5MHz MAX1446 toc29 5.0 MAX1446 toc28 20 DIGITAL POWER-DOWN CURRENT vs. DIGITAL POWER SUPPLY ANALOG POWER-DOWN CURRENT vs.
PAGE 10
-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 Pin Description 10 PIN NAME FUNCTION 1 REFN Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 2 COM Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor. 3, 9, 10 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 4, 5, 8, 11, 14, 30 GND Analog Ground 6 IN+ Positive Analog Input.
PAGE 11
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1446 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code.
PAGE 12
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1446 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider if an application requires a reduced full-scale range.
PAGE 13
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference fIN = 12.5MHz AT -0.5dBFS fIN = 12.5MHz AT -0.5dBFS -50 THD (dBc) SFDR (dBc) 70 60 -60 -70 50 -80 40 20 30 40 50 60 20 70 30 40 50 60 70 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%) Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input) Figure 4a. THD vs. Clock Duty Cycle (Differential Input) 70 70 fIN = 12.5MHz AT -0.5dBFS fIN = 12.5MHz AT -0.
PAGE 14
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 6 also shows the relationship between the input clock parameters and the valid output data. Applications Information Figure 7 shows a typical application circuit containing a single-ended to differential converter.
PAGE 15
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 5V 0.1μF LOWPASS FILTER IN+ MAX4108 RISO 50Ω 0.1μF 300Ω CIN 22pF 0.1μF -5V MAX1446 600Ω 600Ω 300Ω COM 0.1μF 5V 5V 0.1μF 600Ω INPUT 0.1μF LOWPASS FILTER MAX4108 300Ω 0.1μF -5V IN- MAX4108 RISO 50Ω CIN 22pF 300Ω -5V 0.1μF 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion 25Ω IN+ REFP 22pF MAX1446 0.1μF VIN 3 T1 1kΩ VIN 0.1μF 4 RISO IN+ MAX4108 N.C.
PAGE 16
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference 3.3V 0.1μF 3.3V N.C. 0.1μF 2.048V 1 MAX6062 31 0.1μF 2 16.2kΩ 3 32 1 5 162Ω 1μF 4 3 MAX4250 2 10Hz LOWPASS FILTER 29 2 1 100μF 0.1μF 0.1μF REFOUT REFIN REFP MAX1446 N=1 REFN COM 0.1μF 10Hz LOWPASS FILTER 0.1μF N.C. 29 31 32 1 0.1μF 2 0.1μF 0.1μF 2.2μF 10V REFOUT REFIN REFP MAX1446 N = 1000 REFN COM 0.1μF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. Figure 10.
PAGE 17
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference MAX1446 3.3V 0.1μF N.C. 29 31 REFOUT REFIN 1 2.0V 2 32 3.3V 21.5kΩ 3 MAX6066 1 1 47Ω 1/4 MAX4252 2 2 21.5kΩ 3 REFP MAX1446 2.0V AT 8mA 4 11 10μF 6V 330μF 6V 0.1μF 0.1μF N=1 REFN COM 0.1μF 1.47kΩ 1μF 1.5V 3.3V 5 3.3V 1.5V AT 0mA 4 7 47Ω 1/4 MAX4252 0.1μF 6 11 21.5kΩ MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 10μF 6V 330μF 6V 1.47kΩ 1.0V 3.3V 10 1.
PAGE 18
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Keep all signal lines short and free of 90° turns.
PAGE 19
10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference REFP REFIN GND REFOUT D0 D1 D2 D3 TOP VIEW 32 31 30 29 28 27 26 25 REFN 1 24 D4 COM 2 23 OGND VDD 3 22 T.P. GND 4 GND 5 IN+ 6 19 D6 IN- 7 18 D7 GND 8 17 D8 21 OVDD MAX1446 9 10 11 12 13 14 15 16 VDD VDD GND CLK PD GND OE D9 20 D5 TQFP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PAGE 20
MAX1446 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference Revision History REVISION NUMBER REVISION DATE 3 11/07 Various corrections; updated to extended temperature range for automotive applications; replaced TOCs 9–20, 23, 24, 26, 30, 31, 33; updated package outlines. 4 11/08 Updates to the Electrical Characteristics table and notes section.