Datasheet

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General Description

The MAX1449 3.3V, 10-bit analog-to-digital converter

(ADC) features a fully differential input, a pipelined 10-

stage ADC architecture with wideband track-and-hold

(T/H), and digital error correction incorporating a fully dif-

ferential signal path. The ADC is optimized for low-

power, high-dynamic performance in imaging and digital

communications applications. The converter operates

from a single 2.7V to 3.6V supply, consuming only

186mW while delivering a 58.5dB (typ) signal-to-noise

ratio (SNR) at a 20MHz input frequency. The fully differ-

ential input stage has a -3dB 400MHz bandwidth and

may be operated with single-ended inputs. In addition to

low operating power, the MAX1449 features a 5µA

power-down mode for idle periods.

An internal 2.048V precision bandgap reference is

used to set the ADC’s full-scale range. A flexible refer-

ence structure allow’s the user to supply a buffered,

direct, or externally derived reference for applications

requiring increased accuracy or a different input volt-

age range.

Lower speed, pin-compatible versions of the MAX1449

are also available. Refer to the MAX1444 data sheet for

a 40Msps version, the MAX1446 data sheet for a

60Msps version, and the MAX1448 data sheet for 80Msps.

The MAX1449 has parallel, offset binary, CMOS-com-

patible, three-state outputs that can be operated from

1.7V to 3.6V to allow flexible interfacing. The device is

available in a 5mm x 5mm 32-pin TQFP package and is

specified over the extended industrial (-40°C to +85°C)

temperature range.

________________________Applications

Ultrasound Imaging

CCD Imaging

Baseband and IF Digitization

Digital Set-Top Boxes

Video Digitizing Applications

Features

♦ Single 3.3V Operation

♦ Excellent Dynamic Performance

58.5dB SNR at f

= 20MHz

72dBc SFDR at f

= 20MHz

♦ Low Power

62mA (Normal Operation)

5µA (Shutdown Mode)

♦ Fully Differential Analog Input

♦ Wide 2Vp-p Differential Input Voltage Range

♦ 400MHz -3dB Input Bandwidth

♦ On-Chip 2.048V Precision Bandgap Reference

♦ CMOS-Compatible Three-State Outputs

♦ 32-Pin TQFP Package

♦ Evaluation Kit Available (MAX1448 EV Kit)

MAX1449

10-Bit, 105Msps, Single 3.3V, Low-Power

ADC with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

CLK

IN+

CONTROL

PIPELINE ADC

REF SYSTEM +

BIAS

OUTPUT

DRIVERS

REF

REFINREFOUT REFP COM REFN OE

GND

OGND

D9–D0

IN-

T/H

MAX1449

Functional Diagram

19-4802; Rev 2; 9/04

EVALUATION KIT

AVAILABLE

Ordering Information

Pin Configuration appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1449EHJ -40°C to +85°C 32 TQFP

PART SAMPLING SPEED (Msps)

MAX1444 40

MAX1446 60

MAX1448 80

Pin-Compatible, Lower Speed

Selection Table

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Summary of content (21 pages)

PAGE 1
9-4802; Rev 2; 9/04 KIT ATION EVALU E L B AVAILA 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference The MAX1449 3.3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high-dynamic performance in imaging and digital communications applications.
PAGE 2
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.
PAGE 3
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference (VDD = 3.3V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.
PAGE 4
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted.
PAGE 5
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference (VDD = 3.3V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical values are at TA = +25°C.
PAGE 6
Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) 3RD HARMONIC -50 3RD HARMONIC -60 -50 -70 -80 -80 -90 -90 -90 -100 -100 -100 20 30 40 50 60 0 10 20 30 40 50 FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) FFT PLOT (fIN = 19.99MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) -10 -20 2ND HARMONIC -50 -60 3RD HARMONIC SNR = 57.7dB SINAD = 57.
PAGE 7
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference SINGLE-ENDED 54 (d ) 2 -4 -6 -6 -8 -8 10 1 100 10 100 ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER (fIN = 19MHz) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER (fIN = 19MHz) 60 1000 -50 -55 -60 65 55 THD (dBc) SNR (dB) 50 60 -65 -70 45 55 50 -75 40 -12 -9 -6 -3 -80 -12 0 -9 -6 -3 0 ANALOG INPUT POWER (dB FS) ANALOG INPUT POWER (dB FS) SIGNAL-TO-NOISE + DISTORTION vs.
PAGE 8
Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE fIN = 26.1696MHz -64 0.5 MAX1449 toc20 70 MAX1449 toc19 -60 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) fIN = 26.1696MHz 66 MAX1449 toc21 TOTAL HARMONIC DISTORTION vs. TEMPERATURE 0.4 0.3 THD (dBc) -68 -72 INL (LSB) SINAD (dB) 0.
PAGE 9
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference DIGITAL SUPPLY CURRENT vs. TEMPERATURE ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE 9 IOVDD (µA) IVDD (µA) 8 2.60 2.40 6 2.00 35 60 85 0 2.70 2.85 3.00 TEMPERATURE (°C) 3.15 3.30 3.45 3.60 2.0 2.3 2.6 VDD (V) 3.6 MAX1449 toc32 SFDR 75 2.100 MAX1449 toc31 fIN = 50.123MHz 3.3 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY 80 3.0 OVDD (V) 2.
PAGE 10
-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference MAX1449 Pin Description 10 PIN NAME 1 REFN FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 2 COM Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor. 3, 9, 10 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 4, 5, 8, 11, 14, 30 GND Analog Ground 6 IN+ Positive Analog Input.
PAGE 11
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference The MAX1449 uses a 10-stage, fully differential, pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code.
PAGE 12
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference The MAX1449 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, the internal reference output REFOUT can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range.
PAGE 13
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference -50 fIN = 25.123MHz AT -0.5dB FS MAX1449 90 fIN = 25.123MHz AT -0.5dB FS -55 82 74 THD (dBc) SFDR (dBc) -60 66 -65 -70 -75 58 -80 -85 50 35 42 49 56 63 35 70 42 Figure 3a. Spurious Free Dynamic Range vs. Clock Duty Cycle (Differential Input) 62 49 56 63 70 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%) Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle (Differential Input) 64 fIN = 25.123MHz AT -0.
PAGE 14
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference System Timing Requirements Using Transformer Coupling Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1449 samples at the falling edge of the input clock. Output data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 6 also determines the relationship between the input clock parameters and the valid output data.
PAGE 15
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference MAX1449 5V 0.1µF LOWPASS FILTER IN+ MAX4108 RISO 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V MAX1449 600Ω 600Ω 300Ω COM 0.1µF 5V 5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω 0.1µF -5V IN- MAX4108 RISO 50Ω CIN 22pF 300Ω -5V 0.1µF 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit Using the Internal Reference 25Ω IN+ 22pF REFP MAX1449 0.1µF VIN 3 N.C. 5 1 T1 4 0.1µF RISO IN+ MAX4108 2 6 1kΩ VIN COM 2.
PAGE 16
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference 3.3V 0.1µF 3.3V N.C. 0.1µF 2.048V 1 MAX6062 31 0.1µF 2 16.2kΩ 3 32 1 5 162Ω 1µF 4 3 MAX4250 2 10Hz LOWPASS FILTER 29 2 1 100µF 0.1µF 0.1µF REFOUT REFIN REFP MAX1449 N=1 REFN COM 0.1µF 10Hz LOWPASS FILTER 0.1µF N.C. 29 31 32 1 0.1µF 2 0.1µF 0.1µF 2.2µF 10V REFOUT REFIN REFP MAX1449 N = 1000 REFN COM 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. Figure 10.
PAGE 17
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference MAX1449 3.3V 0.1µF N.C. 29 31 REFOUT REFIN 1 2.0V 2 32 3.3V 21.5kΩ 3 MAX6066 1 1 47Ω 1/4 MAX4252 2 2 21.5kΩ 3 REFP MAX1449 2.0V AT 8mA 4 11 10µF 6V 330µF 6V 0.1µF 0.1µF N=1 REFN COM 0.1µF 1.47kΩ 1µF 1.5V 3.3V 5 3.3V 1.5V AT 0mA 4 7 47Ω 1/4 MAX4252 0.1µF 6 11 21.5kΩ MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 10µF 6V 330µF 6V 1.47kΩ 1.0V 3.3V 10 1.
PAGE 18
MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference Grounding, Bypassing, and Board Layout The MAX1449 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND.
PAGE 19
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference CLK Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.
PAGE 20
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 32L TQFP, 5x5x01.0.EPS MAX1449 10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference PACKAGE OUTLINE, 32L TQFP, 5x5x1.
PAGE 21
10-Bit, 105Msps, Single 3.3V, Low-Power ADC with Internal Reference PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm 21-0110 B 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.