Datasheet

DOUT valid timing characteristic. Data should be
clocked into the µP on SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the LSB.
5) With CS/SHDN high, wait at least 60ns (t
CS
) before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output in two 8-bit sequences or continu-
ously. The bytes will contain the result of the conversion
padded with three leading ones and the channel identi-
fication before the MSB. If the serial clock hasn’t been
idled after the last LSB and CS/SHDN is kept low,
DOUT sends trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c).
Two consecutive 8-bit readings are necessary to obtain
the entire 12-bit result from the ADC. DOUT data transi-
tions on the serial clock’s falling edge and is clocked
into the µP on SCLK’s rising edge. The first 8-bit data
stream contains three leading ones, the channel identi-
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 11
• • •
• • •
• • •
CS/SHDN
SCLK
DOUT
t
CL
t
DV
t
CH
t
SCLKS
HIGH-Z HIGH-Z
t
CS
t
DO
t
TR
Figure 7. Detailed Serial-Interface Timing Sequence
MAX144
MAX145
CS/SHDN
SCLK
DOUT
I/O
SK
SI
MICROWIRE
CS/SHDN
SCLK
DOUT
I/O
SCK
MISO
V
DD
SS
MAX144
MAX145
SPI
Figure 8a. SPI Connections
8b. MICROWIRE Connections
CHID D11 D10 D9 D8
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3
HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ 2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB LSB
D2 D1 D0
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)