Datasheet

MAX144/MAX145
fication, and the first four data bits starting with the
MSB. The second 8-bit data stream contains the
remaining bits, D7 through D0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX144/MAX145 support a maxi-
mum f
SCLK
of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX144. Figure 9b shows
the QSPI interface timing.
PIC16 with SSP Module and PIC17 Interface
The MAX144/MAX145 are compatible with a PIC16/
PIC17 controller (µC), using the synchronous serial-port
(SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains three leading ones,
the channel identification, and the first four data bits
starting with the MSB. The second 8-bit data stream
contains the remaining bits, D7 through D0.
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
12 ______________________________________________________________________________________
CHID D11 D10 D9 D8
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3
HIGH-Z
DOUT
CS/SHDN
SCLK
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB
LSB
D2 D1 D0
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CS/SHDN
SCLK
DOUT
CS
SCK
MISO
V
DD
SS
QSPI
MAX144
MAX145
Figure 9a. QSPI Connections
Table 2. Detailed SSPCON Register Contents
CONTROL BIT
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detect Bit
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
SSPM3 BIT3 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
f
CLK
= f
OSC
/ 16.
SSPEN BIT5 1
Synchronous Serial-Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
X = Don’t care