Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX1471ATJ+

General Description

The MAX1471 low-power, CMOS, superheterodyne, RF

dual-channel receiver is designed to receive both ampli-

tude-shift-keyed (ASK) and frequency-shift-keyed (FSK)

data without reconfiguring the device or introducing any

time delay normally associated with changing modula-

tion schemes. The MAX1471 requires few external com-

ponents to realize a complete wireless RF digital data

receiver for the 300MHz to 450MHz ISM bands.

The MAX1471 includes all the active components

required in a superheterodyne receiver including: a low-

noise amplifier (LNA), an image-reject (IR) mixer, a fully

integrated phase-locked loop (PLL), local oscillator

(LO), 10.7MHz IF limiting amplifier with received-signal-

strength indicator (RSSI), low-noise FM demodulator,

and a 3V voltage regulator. Differential peak-detecting

data demodulators are included for both the FSK and

ASK analog baseband data recovery. The MAX1471

includes a discontinuous receive (DRX) mode for low-

power operation, which is configured through a serial

interface bus.

The MAX1471 is available in a 32-pin thin QFN package

and is specified over the automotive -40°C to +125°C

temperature range.

Applications

Automotive Remote Keyless Entry (RKE)

Tire Pressure Monitoring Systems

Garage Door Openers

Wireless Sensors

Wireless Keys

Security Systems

Medical Systems

Home Automation

Local Telemetry Systems

Features

o ASK and FSK Demodulated Data on Separate

Outputs

o Specified over Automotive -40°C to +125°C

Temperature Range

o Low Operating Supply Voltage Down to 2.4V

o On-Chip 3V Regulator for 5V Operation

o Low Operating Supply Current

7mA Continuous Receive Mode

1.1µA Deep-Sleep Mode

o Discontinuous Receive (DRX) Low-Power

Management

o Fast-On Startup Feature < 250µs

o Integrated PLL, VCO, and Loop Filter

o 45dB Integrated Image Rejection

o RF Input Sensitivity*

ASK: -114dBm

FSK: -108dBm

o Selectable IF BW with External Filter

o Programmable Through Serial User Interface

o RSSI Output and High Dynamic Range with AGC

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

________________________________________________________________

Maxim Integrated Products

31 30 29 28 27 26

9 101112131415

MAX1471

THIN QFN

TOP VIEW

DSA+

DSA-

OPA+

DFA

XTAL2

XTAL1

AVDD

LNAIN

PDMAXA

PDMINA

ADATA

HVIN

SCLK

DIO

FDATA

DVDD

DGND

DFF

OPF+

DSF+

DSF-

PDMAXF

PDMINF

IFIN-

AGND

IFIN+

MIXOUT

MIXIN-

MIXIN+

LNAOUT

LNASRC

Pin Configuration

19-3272; Rev 4; 9/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BW

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX1471ATJ/V+ -40°C to +125°C 32 Thin QFN-EP**

Denotes a lead(Pb)-free/RoHS-compliant package.

/V denotes an automotive qualified part.

EP = Exposed pad.

Summary of content (26 pages)

PAGE 1
9-3272; Rev 4; 9/11 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver The MAX1471 low-power, CMOS, superheterodyne, RF dual-channel receiver is designed to receive both amplitude-shift-keyed (ASK) and frequency-shift-keyed (FSK) data without reconfiguring the device or introducing any time delay normally associated with changing modulation schemes. The MAX1471 requires few external components to realize a complete wireless RF digital data receiver for the 300MHz to 450MHz ISM bands.
PAGE 2
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver ABSOLUTE MAXIMUM RATINGS High-Voltage Supply, HVIN to DGND ......................-0.3V, +6.0V Low-Voltage Supply, AVDD and DVDD to AGND ....-0.3V, +4.0V SCLK, DIO, CS, ADATA, FDATA ...................................(DGND - 0.3V) to (HVIN + 0.3V) All Other Pins............................(AGND - 0.3V) to (AVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ...
PAGE 3
15MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver (Typical Application Circuit, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = +3.0V, fRF = 434 MHz, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Input-High Leakage Current Input-Low Leakage Current Input Capacitance SYMBOL CONDITIONS MIN TYP MAX UNITS -20 µA IIH (Note 2) IIL (Note 2) 20 µA CIN (Note 2) 2.
PAGE 4
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VHVIN = +3.0V, fRF = 434 MHz, TA = +25°C, unless otherwise noted.
PAGE 5
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 Typical Operating Characteristics (Typical Application Circuit, VAVDD = VDVDD = VHVIN = +3.0V, fRF = 434MHz, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. RF FREQUENCY 7.8 6.8 +25°C +85°C 7.4 7.2 7.0 6.8 6.6 +25°C 6.4 -40°C +105°C +125°C 7.6 12 10 DEEP-SLEEP CURRENT (µA) 7.2 6.4 8.0 SUPPLY CURRENT (mA) +85°C 7.6 SUPPLY CURRENT (mA) +125°C MAX1471 toc02 +105°C MAX1471 toc01 8.0 DEEP-SLEEP CURRENT vs.
PAGE 6
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Typical Operating Characteristics (continued) (Typical Application Circuit, VAVDD = VDVDD = VHVIN = +3.0V, fRF = 434MHz, TA = +25°C, unless otherwise noted.) 1.2 0.5 0.9 -0.5 0.6 -1.5 DELTA 0.3 DELTA (%) RSSI (V) 1.5 -2.5 0 -3.5 -90 -70 -50 -30 -10 1.6 1.2 0.8 0.4 IMAGE REJECTION vs. TEMPERATURE 10 10.5 10.6 10.7 10.8 10.
PAGE 7
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION MAX1471 toc17 fRF = 315MHz L1 = 0nH REAL IMPEDANCE (Ω) -200 60 IMAGINARY IMPEDANCE 50 -225 40 -250 30 -275 20 -300 10 0 10 1 -175 -200 60 IMAGINARY IMPEDANCE 50 -250 -275 30 REAL IMPEDANCE 20 10 -350 100 0 INDUCTIVE DEGENERATION (nH) PHASE NOISE vs.
PAGE 8
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 Pin Description (continued) 8 PIN NAME FUNCTION 6 XTAL1 1st Crystal Input 7 AVDD Analog Power-Supply Voltage for RF Sections. AVDD is connected to an on-chip +3.0V low-dropout regulator. Decouple to AGND with a 0.1µF capacitor. 8 LNAIN Low-Noise Amplifier Input Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to AGND to set LNA input impedance.
PAGE 9
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver LNAIN 8 LNASRC 9 LNAOUT MIXIN+ MIXIN- 10 11 12 MIXOUT IFIN13 IFIN+ 15 16 IMAGE REJECTION 0° LNA IF LIMITING AMPS Σ 90° RSSI AGND 14 XTAL1 6 XTAL2 5 CRYSTAL OSCILLATOR DIVIDE BY 32 VCO PHASE DETECTOR LOOP FILTER RDF1 100kΩ 4 DFA 3 OPA+ 2 DSA+ RDF2 100kΩ CS 26 FSK SERIAL INTERFACE, CONTROL REGISTERS, AND POLLING TIMER DIO 27 ASK FSK DEMODULATOR ASK DATA FILTER SCLK 28 DVDD 24 31 PDMINA DGND 23 RDF1 100k
PAGE 10
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Detailed Description The MAX1471 CMOS superheterodyne receiver and a few external components provide a complete ASK/FSK receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates as high as 33kbps using Manchester Code (66kbps nonreturn to zero) can be achieved. The MAX1471 is designed to receive binary FSK or ASK data on a 300MHz to 450MHz carrier.
PAGE 11
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver FSK Demodulator The FSK demodulator uses an integrated 10.7MHz PLL that tracks the input RF modulation and determines the difference between frequencies as logic-level ones and zeros. The PLL is illustrated in Figure 1. The input to the PLL comes from the output of the IF limiting amplifiers. The PLL control voltage responds to changes in the frequency of the input signal with a nominal gain of 2.2mV/kHz.
PAGE 12
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver ASK DATA OUT VDD 3.
PAGE 13
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 Table 1. Component Values for Typical Application Circuit COMPONENT VALUE FOR 433.92MHz RF VALUE FOR 315MHz RF DESCRIPTION (%) C3 220pF 220pF 10 C4 470pF 470pF 5 C5 0.047µF 0.047µF 10 C6 0.1µF 0.1µF 10 C7 100pF 100pF 5 C8 100pF 100pF 5 C9 1.0pF 2.2pF ±0.
PAGE 14
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Table 2. Coefficients to Calculate CF1 and CF2 FILTER TYPE a b Butterworth (Q = 0.707) 1.414 1.000 Bessel (Q = 0.577) 1.3617 0.618 MAX1471 RSSI OR FSK DEMOD 100kΩ DSA+ DSF+ OPA+ OPF+ 100kΩ DFA DFF CF2 CF1 Figure 3. Sallen-Key Lowpass Data Filter MAX1471 DATA SLICER ADATA FDATA DSADSFC DSA+ DSF+ R Figure 4.
PAGE 15
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 MAX1471 DATA SLICER ADATA FDATA MAXIMUM PEAK DETECTOR MINIMUM PEAK DETECTOR PDMAXA PDMAXF C R R PDMINA PDMINF C Figure 5. Generating Data-Slicer Threshold Using the Peak Detectors MINIMUM PEAK DETECTOR PDMINA PDMINF BASEBAND FILTER TRK_EN = 1 MAXIMUM PEAK DETECTOR TO SLICER INPUT PDMAXA PDMAXF MAX1471 TRK_EN = 1 Figure 6. Peak-Detector Track Enable Power-Supply Connections The MAX1471 can be powered from a 2.4V to 3.
PAGE 16
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Serial Control Interface Communication Protocol The MAX1471 can use a 4-wire interface or a 3-wire interface (default). In both cases, the data input must follow the timing diagrams shown in Figures 8 and 9. Note that the DIO line must be held LOW while CS is high. This is to prevent the MAX1471 from entering discontinuous receive mode if the DRX bit is high.
PAGE 17
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 CS SCLK DIO C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D2 D1 D0 DATA ADDRESS COMMAND D3 Figure 9.
PAGE 18
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver CS SCLK DIO 0 0 1 0 A3 READ COMMAND A2 A1 A0 0 0 0 0 ADDRESS 0 0 0 0 R7 R6 R5 DATA R4 R3 R2 R1 R0 R7 R0 REGISTER DATA REGISTER DATA 16 BITS OF DATA CS SCLK DIO 0 0 1 READ COMMAND 0 A3 A2 A1 A0 0 0 0 ADDRESS 0 0 DATA 0 0 0 R7 R6 R5 R4 R3 R2 R1 A3 REGISTER DATA 8 BITS OF DATA Figure 11. Read Command in 3-Wire Interface Table 3.
PAGE 19
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver REGISTER A[3:0] REGISTER NAME 0x0 Power configuration 0x1 Configuration Sets options for the device such as output enables, off-timer prescale, and discontinuous receive mode (see Table 7). 0x2 Control Controls AGC lock, peak-detector tracking, as well as polling timer and FSK calibration (see Table 8).
PAGE 20
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Table 5.
PAGE 21
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver MAX1471 Table 6.
PAGE 22
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Table 7. Configuration Register (Address: 0x1) BIT ID BIT NAME BIT LOCATION (0 = LSB) POWER-UP STATE X Don’t care 7 0 Don’t care. 1 0 = LNA low-gain state. 1 = LNA high-gain state. For manual gain control, enable the AGC (AGC_EN = 1), set LNA gain state to desired setting, then disable the AGC (AGC_EN = 0).
PAGE 23
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver BIT ID BIT NAME BIT LOCATION (0 = LSB) POWER-UP STATE X None 7 Don’t care AGCLOCK AGC lock 6 0 X None 5, 4 FSKTRK_EN FSK peak detector track enable 3 0 Enables the tracking mode of the FSK peak detectors when FSKTRK_EN = 1. (See the Peak Detectors section.) ASKTRK_EN ASK peak detector track enable 2 0 Enables the tracking mode of the ASK peak detectors when ASKTRK_EN = 1. (See the Peak Detectors section.
PAGE 24
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver CS DIO tOFF tOFF tCPU tCPU tLOW tRF tRF ADATA OR FDATA Figure 12. DRX Mode Sequence of the MAX1471 Table 10. Off-Timer (tOFF) Configuration PRESCALE1 PRESCALE0 tOFF TIME BASE (1 LSB) MIN tOFF REG 0x4 = 0x00 REG 0x5 = 0x01 MAX tOFF REG 0x4 = 0xFF REG 0x5 = 0xFF 0 0 120µs 120µs 7.86s 0 1 480µs 480µs 31.46s 1 0 1920µs 1.92ms 2 min 6s 1 1 7680µs 7.68ms 8 min 23s Table 11.
PAGE 25
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 26
MAX1471 315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver Revision History REVISION NUMBER REVISION DATE 2 11/10 Updated Ordering Information, Absolute Maximum Ratings, AC Electrical Characteristics, and Package Information 3 12/10 Updated Ordering Information and AC Electrical Characteristics 4 9/11 Added text to describe unused PD pins, updated Typical Application Circuit, eliminated inductor vendor in Table 1, updated the Peak Detectors section, and added Control Interface Consid