Datasheet

AVAILABLE
EVALUATION KIT AVAILABLE
Functional Diagrams
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and
ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
General Description
The MAX1473 fully integrated low-power CMOS super-
heterodyne receiver is ideal for receiving amplitude-
shift-keyed (ASK) data in the 300MHz to 450MHz
frequency range. Its signal range is from -114dBm to
0dBm. With few external components and a low-current
power-down mode, it is ideal for cost- and power-sensi-
tive applications typical in the automotive and consumer
markets. The chip consists of a low-noise amplifier
(LNA), a fully differential image-rejection mixer, an on-
chip phase-locked-loop (PLL) with integrated voltage-
controlled oscillator (VCO), a 10.7MHz IF limiting
amplifier stage with received-signal-strength indicator
(RSSI), and analog baseband data-recovery circuitry.
The MAX1473 also has a discrete one-step automatic
gain control (AGC) that drops the LNA gain by 35dB
when the RF input signal is greater than -57dBm.
The MAX1473 is available in 28-pin TSSOP and 32-pin
thin QFN packages. Both versions are specified for the
extended (-40°C to +85°C) temperature range.
Applications
Automotive Remote Keyless Entry Security Systems
Garage Door Openers Home Automation
Remote Controls Local Telemetry
Wireless Sensors
Systems
Features
o Optimized for 315MHz or 433MHz ISM Band
o Operates from Single 3.3V or 5.0V Supplies
o High Dynamic Range with On-Chip AGC
o Selectable Image-Rejection Center Frequency
o Selectable x64 or x32 f
LO
/f
XTAL
Ratio
o Low 5.2mA Operating Supply Current
o < 2.5µA Low-Current Power-Down Mode for
Efficient Power Cycling
o 250µs Startup Time
o Built-In 50dB RF Image Rejection
o Receive Sensitivity of -114dBm
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XTAL2
PWRDN
PDOUT
DATAOUT
V
DD5
DSP
AGCDIS
DFFB
OPP
DSN
DFO
IFIN2
IFIN1
XTALSEL
DVDD
DGND
MIXOUT
IRSEL
AGND
MIXIN2
MIXIN1
AVDD
LNAOUT
AGND
LNASRC
LNAIN
AVDD
XTAL1
TSSOP
THIN QFN
TOP VIEW
MAX1473
32
31
30
29
28
27
26
LNASRC
LNAIN
AVDD
XTAL1
XTAL2
PWRDN
PDOUT
25 N.C.
9
10
11
12
13
14
15
MIXOUT
DGND
DVDD
AGCDIS
N.C.
XTALSEL
IFIN1
16IFIN2
17
18
19
20
21
22
23
DFO
DSN
OPP
DFFB
N.C.
DSP
V
DD5
8
7
6
5
4
3
2
IRSEL
AGND
MIXIN2
MIXIN1
AVDD
LNAOUT
AGND
MAX1473
1N.C.
24 DATAOUT
+
+
PART TEMP RANGE PIN-PACKAGE
MAX1473EUI+ -40°C to +85°C 28 TSSOP
MAX1473ETJ+ -40°C to +85°C 32 Thin QFN-EP*
Pin Configurations
Ordering Information
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
MAX1473
19-2748; Rev 6; 1/12

Summary of content (16 pages)