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MAX14824

IO-Link Master Transceiver

Typical Operating Circuits

19-5788; Rev 3; 5/12

Typical Operating Circuits continued at end of data sheet.

General Description

The MAX14824 is an IO-Link

master interface that inte-

grates an IO-Link physical layer transceiver with an

auxiliary digital input and two linear regulators. High port

count IO-Link master applications are supported through

in-band SPI addressing, and the 12MHz SPI interface

minimizes host controller access times. In-band address-

ing and selectable SPI addresses enable cascading up

to 16 devices.

The device supports all the IO-Link data rates and fea-

tures slew-rate-controlled drivers to reduce EMI. The

driver is guaranteed to drive up to 300mA (min) load

currents. Internal wake-up circuitry automatically deter-

mines the correct wake-up polarity, allowing for the use

of simple UARTs for wake-up pulse generation.

The MAX14824 is available in a 4mm x 4mm, 24-pin

TQFN package with exposed pad, and operates over the

extended -40NC to +105NC temperature range.

Applications

IO-Link Master Controllers

PLC Fieldbus Gateways

High Port Count IO-Link Masters

24V Digital Inputs and Outputs

Features

S IO-Link v.1.0 and v.1.1 Physical Layer Compliant

S Supports COM1, COM2, and COM3 Data Rates

S Push-Pull, High-Side, or Low-Side Outputs

S 300mA C/Q Output Drive

S 1µF C/Q Load Drive Capability

S Generates 500mA Wake-Up Pulse

S Automatic Wake-Up Pulse Polarity

S Auxiliary Digital Input

S 5V and 3.3V Linear Regulators

S SPI Interface for Configuration and Monitoring

S SPI-Based Chip Addressing

S EMI Emission Control Through Slew-Controlled

Driver

S Reverse-Polarity Protection on DI

S Short-Circuit Protection on C/Q

S High Temperature Warning and Thermal Shutdown

S Extensive Fault Monitoring and Reporting

S -40NC to +105NC Operating Temperature Range

S 4mm x 4mm TQFN Package

IO-Link is a registered trademark of Profibus User Organization (PNO).

Ordering Information appears at end of data sheet.

For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX14824.related

EVALUATION KIT AVAILABLE

MAX14824

1μF

1μF 0.1μF

270pF

LDOIN

C/Q C/Q

SPI

GNDA3A2A1A0GND

24V

LDO33V

TXQ

IO-LINK

CONTROLLER

WUENGPO

RXRX

TXCTX

TXENRTS

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Summary of content (28 pages)

PAGE 1
9-5788; Rev 3; 5/12 EVALUATION KIT AVAILABLE MAX14824 IO-Link Master Transceiver General Description Features The MAX14824 is an IO-LinkM master interface that integrates an IO-Link physical layer transceiver with an auxiliary digital input and two linear regulators. High port count IO-Link master applications are supported through in-band SPI addressing, and the 12MHz SPI interface minimizes host controller access times. In-band addressing and selectable SPI addresses enable cascading up to 16 devices.
PAGE 2
MAX14824 IO-Link Master Transceiver Functional Diagram LDO33 V5 LDOIN UV UV MONITOR 3.
PAGE 3
MAX14824 IO-Link Master Transceiver ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND, unless otherwise specified.) VCC.........................................................................-0.3V to +40V LDOIN.....................................................................-0.3V to +40V V5........................0.3V to the lesser of (VLDOIN + 0.3V) and +6V LDO33 ..................... -0.3V to the lesser of (V5 + 0.3V) and +6V VL..................................................................
PAGE 4
MAX14824 IO-Link Master Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40NC to +105NC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2) PARAMETER LDOIN Supply Current V5 Output Voltage Range SYMBOL ILDOIN V5 CONDITIONS MIN VLDOIN = 24V, C/Q as input, no load on V5 or LDO33 No load on V5, 7V P VLDOIN P 36V 4.
PAGE 5
MAX14824 IO-Link Master Transceiver DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.
PAGE 6
MAX14824 IO-Link Master Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS TYP MAX UNITS 0.1 2 Fs HiSlew = 1 0.4 0.85 HiSlew = 0 1.5 4 Push-pull or low-side (NPN) configuration, Figure 1 HiSlew = 1 0.4 0.85 HiSlew = 0 1.
PAGE 7
MAX14824 IO-Link Master Transceiver AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 18V to 36V, VL = 2.3V to 5.5V, VGND = 0V; all logic inputs at VL or GND; TA = -40oC to +105oC, unless otherwise noted. Typical values are at VCC = 24V, VL = 3.3V, and TA = +25oC, unless otherwise noted.) (Note 2) PARAMETER SYMBOL SDI Setup Time tDS Output Data Propagation Delay tDO SDO Rise and Fall Times Minimum CS Pulse CONDITIONS MIN tFT tCSW TYP MAX 10 76.
PAGE 8
MAX14824 IO-Link Master Transceiver TXEN TXC C/Q MAX14824 TXQ 3.3nF 5kΩ GND VL TXEN 0V VL TXC AND TXQ 50% 0V tPDHL tPDLH C/Q tFALL VCC 90% 50% 10% 0V tRISE Figure 1. Driver Polarity and Timing VCC 5kΩ TXEN C/Q VL MAX14824 TXC 3.3nF TXQ GND VL TXEN 0V tDISH tENL VCC C/Q 10% 10% 0V Figure 2.
PAGE 9
MAX14824 IO-Link Master Transceiver TXEN C/Q MAX14824 TXC 3.3nF 5kΩ TXQ GND VL TXEN 0V tDISL tENH C/Q VCC 90% 90% 0V Figure 3. Driver Enable High and Disable Low Timing RX OR LI C/Q OR DI 15pF MAX14824 TXEN GND VCC C/Q OR DI 50% tPRLH 0V tPRHL VL RX OR LI 50% 0V Figure 4.
PAGE 10
MAX14824 IO-Link Master Transceiver WUEN tWUEN, H tWUEN, S TXC AND TXQ 80µs t1 t2 C/Q X WAKE-UP PULSE Figure 5. Wake-Up Generation CS tCSS tCSH tCH tCSH tCL SCLK tDS tDH SDI tDO SDO Figure 6.
PAGE 11
MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) TA = -40°C 23 5 VOL_C/Q (V) TA = +85°C 21 TA = +105°C 20 19 4 TA = +105°C 3 TA = +85°C 2 1 TXEN = VL TCX = TXQ = GND 0 1.50 TA = -40°C 0 100 200 300 400 500 600 700 800 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) C/Q DRIVER PROPAGATION DELAY vs. TEMPERATURE (HiSlew = 0) C/Q DRIVER PROPAGATION DELAY vs.
PAGE 12
MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) RECEIVER PROPAGATION DELAY vs. TEMPERATURE (RxFilter = 0) 350 C/Q TO RX MAX14824 toc08 DI TO LI 450 400 350 300 tPRHL (ns) tPRHL (ns) 450 400 500 MAX14824 toc07 500 C/Q RECEIVER PROPAGATION DELAY vs.
PAGE 13
MAX14824 IO-Link Master Transceiver Typical Operating Characteristics (continued) (VCC = 24V, LDOIN = VCC, VL = LDO33, C/Q is in push-pull configuration, TA = +25NC, unless otherwise noted.) V5 LOAD REGULATION LDO33 LOAD REGULATION -0.2 -0.1 TA = -40°C -0.2 TA = +25°C -0.3 MAX14824 toc13 -0.1 % VOLTAGE CHANGE 0 % VOLTAGE CHANGE 0 MAX14824 toc12 0.1 TA = +85°C TA = -40°C -0.3 -0.4 TA = +25°C -0.5 -0.6 TA = +85°C -0.7 -0.8 -0.4 -0.9 -0.5 -1.
PAGE 14
MAX14824 IO-Link Master Transceiver Pin Configuration UV LI A2 WUEN RX TXEN TOP VIEW 18 17 16 15 14 13 DI 19 12 TXC GND 20 11 TXQ C/Q 21 10 A3 MAX14824 A1 22 VCC 23 *EP + 1 2 3 4 5 6 LDOIN V5 LDO33 IRQ SCLK CS A0 24 9 VL 8 SDI 7 SDO TQFN (4mm × 4mm) *CONNECT EXPOSED PAD TO GND. Pin Description PIN NAME 1 LDOIN 2 V5 3 LDO33 4 IRQ 5 SCLK FUNCTION 5V Linear-Regulator Input. Bypass LDOIN to GND with a 0.1FF ceramic capacitor.
PAGE 15
MAX14824 IO-Link Master Transceiver Pin Description (continued) PIN NAME FUNCTION Receiver Output. RX is the inverse logic level of C/Q. RX is always high when the RxDis bit in the CQConfig register is set to 1. 14 RX 15 WUEN 16 A2 Chip-Select Address Input 2. Do not leave A2 unconnected. 17 LI Logic Output of 24V DI Logic Input. LI is the inverse logic of DI. LI is referenced to VL. 18 UV Open-Drain Undervoltage Indicator Output. UV is active high.
PAGE 16
MAX14824 IO-Link Master Transceiver The HiSlew bit increases the slew rate of the C/Q driver output. Set HiSlew to 1 for data rates of 230kbps or higher. Set HiSlew to 0 to reduce the C/Q driver slew rate and reduce EMI emission and reflections. The C/Q receiver is always on. Disable the RX output through the RxDis bit in the CQConfig register. Set the RxDis bit to 1 to set the RX output high. Set the RxDis bit to 0 for normal receive operation.
PAGE 17
MAX14824 IO-Link Master Transceiver Wake-Up Generation The MAX14824 features automatic wake-up polarity generation functionality that can be initiated through hardware or software. The following conditions must be met prior to automatic wake-up polarity generation to ensure proper functionality: • WUEN is low • TXEN is low and C/QDEn = 0 • Q=0 • TXC and TXQ are both high Drive WUEN high to enable the automatic wake-up polarity generation circuitry in the device.
PAGE 18
MAX14824 IO-Link Master Transceiver Register Functionality The device has four 8-bit-wide registers for configuration and monitoring (Table 1). R1 and R0 are the register address. Table 1.
PAGE 19
MAX14824 IO-Link Master Transceiver BIT NAME DESCRIPTION D2 UV33Int Internal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and the UV33En bit (in the Mode register) are set when VLDO33 falls below the 2.4V LDO33 undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ. Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for UV33Int.
PAGE 20
MAX14824 IO-Link Master Transceiver CQConfig Register [R1, R0] = [0,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 RxFilter HiSlew C/Q_N/P C/Q_PP C/QDEn Q RxDis C/QLoad Read/Write R/W R/W R/W R/W R/W R/W R/W R/W POR State 0 0 0 0 0 0 0 0 Bit Name Use the CQConfig register to control the C/Q receiver and driver parameters. All bits in the CQConfig register are read-write and are set to 0 at power-up. BIT NAME DESCRIPTION D7 RxFilter C/Q and DI Receiver Filter Control.
PAGE 21
MAX14824 IO-Link Master Transceiver Table 4. C/QDEn and TXEN C/Q Driver Control TXQ TXC C/QDEn TXEN C/Q DRIVER 0 Low Disabled X High Enabled 1 X Enabled C/Q Q Figure 7. Equivalent C/Q Logic X = Don’t care. Table 5.
PAGE 22
MAX14824 IO-Link Master Transceiver Mode Register [R1, R0] = [1,1] Bit D7 D6 D5 D4 D3 D2 D1 D0 Bit Name RST WuEnBit X C/QFault UV24 OTemp UV33En LDO33Dis Read/Write R/W R/W R/W R R R R/W R/W POR State 0 0 0 0 0 0 0 0 X = Unused bits. Use the Mode register to reset the device and manage the 3.3V LDO. The Mode register has bits that represent the current status of fault conditions.
PAGE 23
MAX14824 IO-Link Master Transceiver Table 6. Auto Wake-Up Polarity Generation WuEnBit WUEN 0 Low Normal operation MODE 0 High Wake-up generation mode 1 Low Wake-up generation mode 1 High Wake-up generation mode for the device is 12MHz. The SPI interface complies with clock polarity CPOL = 0 and clock phase CPHA = 0 (see Figure 8 and Figure 9). SPI Interface The device communicates through an SPI-compatible 4-wire serial interface.
PAGE 24
MAX14824 IO-Link Master Transceiver Address Selection The device includes four chip-select address inputs, A0–A3, allowing up to 16 devices on a single bus. Drive the address inputs high or low to program the device address as shown in Table 7. Do not leave any address input unconnected. Table 7.
PAGE 25
MAX14824 IO-Link Master Transceiver EN IN MAX17501 LX GND FB 3.3V 1μF 1μF 10kΩ VCC GPIO2 UV VL TXQ LDO33 V5 LDOIN VCC 270pF SPI C/Q GPIO1 MICROCONTROLLER GND RX WUEN TXC RTS TXEN GPIO3 LI 1 2 RX TX L+ 270pF MAX14824 DI 1nF 4 3 L- GND Figure 12. Use an External Supply to Power the MAX14824 External Power The device is powered by VCC and the 5V regulator, V5. VL is a reference voltage input to set the logic levels of the microcontroller interface.
PAGE 26
MAX14824 IO-Link Master Transceiver Typical Operating Circuits (continued) IO-LINK QUAD MASTER APPLICATION MISO MOSI CONTROLLER SCLK CS1 CS2 MAX14824 RST PORT 1 RX TXC TXEN ADDR 1 VEXT MAX14824 RST CS SCLK MOSI MISO TX0 RX0 RTS0 GPIO1 GPIO5 GPIO9 MAX14830 TX3 RX3 RTS3 XIN RX TXC TXEN TX1 RX1 RTS1 TX2 RX2 RTS2 GPIO13 PORT 2 ADDR 2 MAX14824 PORT 3 RX TXC TXEN ADDR 3 XOUT MAX14824 PORT 1 RX TXC TXEN ADDR 4 26
PAGE 27
MAX14824 IO-Link Master Transceiver Ordering Information PART TEMP RANGE PIN-PACKAGE MAX14824GTG+ -40NC to +105NC 24 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 28
MAX14824 IO-Link Master Transceiver Revision History REVISION NUMBER REVISION DATE 0 3/11 Initial release 6/11 Changed DI threshold to accommodate all three types of industrial sensors, added 24V supply connection in Figure 13 8/11 Corrected IO-Link trademark. Corrected block description in Functional Diagram. Corrected C/Q minimum and maximum ratings in the Absolute Maximum Ratings section. Corrected ICC maximum value and shuffled row parameters in the Electrical Characteristics Table.