Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX14830ETM+

Quad Serial UART with 128-Word FIFOs

MAX14830

EVALUATION KIT AVAILABLE

19-5547; Rev 3; 1/13

General Description

The MAX14830 is an advanced quad universal asyn-

chronous receiver-transmitter (UART), each UART hav-

ing 128 words of receive and transmit first-in/first-out

(FIFO) and a high-speed serial peripheral interface

(SPIK) or I

C controller interface. A PLL and fractional

baud-rate generators allow a high degree of flexibility in

baud-rate programming and reference clock selection.

Each of the four UARTs is selected by in-band SPI/I

addressing. Logic-level translation on the transceiver

and controller interfaces allows ease of interfacing to

microcontrollers, FPGAs, and transceivers that are pow-

ered by differing supply voltages.

Extensive features simplify transceiver control in half-

duplex communication applications. The MAX14830

features the ability to synchronize the start of individual

UART’s transmission by SPI-based triggering. On-board

timers allow programming of delays between transmit-

ters as well as clock generation on GPIOs.

The 128-word FIFOs have advanced FIFO control reduc-

ing host processor data flow management.

The MAX14830 is available in a 48-pin TQFN (7mm x

7mm) package and is specified to operate over the

extended -40NC to +85NC temperature range.

Applications

Industrial Control Systems

Programmable Logic Controllers (PLC)

IO-Link Master Controllers

Automotive Infotainment Systems

Medical Systems

Point-of-Sales Systems

Airplane Communication Buses

Features

S SPI Up to 26MHz Clock Rate

S Fast-Mode Plus (Fm+) I

C Interface Up to 1MHz

S 128-Word Transmit and Receive FIFOs Per UART

S 6Mbaud (max) Data Rate in 16x Sampling Mode

S 12/24Mbaud (max) Data Rate in 2x/4x Rate Modes

S Fractional Baud-Rate Generators, Predivider, and

Phase-Locked Loop (PLL)

S Transmitter Synchronization Through SPI

Commands

S Four Timers Routed to GPIOs

S Automatic Hardware Flow Control Using RTS_

and CTS_ Outputs and Inputs

S Automatic Software Flow Control (XON/XOFF)

S Auto Transceiver Direction Control

S Programmable Setup and Hold Times for

Transceiver Control

S Auto Transmitter Disable

S Half-Duplex Echo Suppression

S Special Character Detection

S 9-Bit Multidrop Mode Address Detection and

Filtering

S SIR- and MIR-Compliant IrDA

Encoder/Decoders

S 16 Flexible GPIOs with 20mA Drive Capability

S +2.35V to +3.6V Supply Range

S Logic-Level Translation Down to 1.61V on

Controller and Transceiver Interfaces

S Small TQFN (7mm x 7mm) Package

Ordering Information

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

SPI is a trademark of Motorola, Inc.

IrDA is a registered service mark of Infrared Data Association

Corporation.

Typical Operating Circuits appear at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX14830ETM+

-40NC to +85NC

48 TQFN-EP*

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

Summary of content (68 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX14830 Quad Serial UART with 128-Word FIFOs General Description The MAX14830 is an advanced quad universal asynchronous receiver-transmitter (UART), each UART having 128 words of receive and transmit first-in/first-out (FIFO) and a high-speed serial peripheral interface (SPIK) or I2C controller interface. A PLL and fractional baud-rate generators allow a high degree of flexibility in baud-rate programming and reference clock selection.
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MAX14830 Quad Serial UART with 128-Word FIFOs TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAX14830 Quad Serial UART with 128-Word FIFOs TABLE OF CONTENTS (continued) AutoRTS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AutoCTS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIFO Interrupt Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAX14830 Quad Serial UART with 128-Word FIFOs LIST OF FIGURES Figure 1. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAX14830 Quad Serial UART with 128-Word FIFOs LIST OF TABLES Table 1. UART GPIO Assignments for GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 2. StopBits Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 3. Length_ Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAX14830 Quad Serial UART with 128-Word FIFOs LIST OF REGISTERS RHR—Receive Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THR—Transmit Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQEn—IRQ Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAX14830 Quad Serial UART with 128-Word FIFOs Functional Diagram V18 VA VL LDOEN VEXT TX0 TRANSMITTER SYNC LDO RX0 CTS0 LOGIC-LEVEL TRANSLATION RTS0 UARTO 4 GPIO0 SPI/I2C GPIO3 TX1 MOSI/A1 RX1 SPI AND I2C INTERFACE MISO/SDA CTS1 CS/A0 SCLK/SCL REGISTERS AND CONTROL RST IRQ UART2 RTS1 LOGIC-LEVEL TRANSLATION UART1 GPIO4 GPIO7 TX2 RX2 CTS2 RTS2 GPIO8 GPIO11 TX3 MAX14830 RX3 CTS3 4 XIN XOUT UART3 DIVIDER PLL AGND Maxim Integrated RTS3 GPIO12 CRYSTAL OSCILLATOR FRACTIONAL BA
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MAX14830 Quad Serial UART with 128-Word FIFOs ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND.) VL, VA, VEXT, XIN................................................. -0.3V to +4.0V V18, XOUT............ -0.3V to the lesser of (VA + 0.3V) and +2.0V RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, SPI/I2C................... -0.3V to (VL + 0.3V) TX0, RX0, CTS0, GPIO0, GPIO1, GPIO2, GPIO3...................................... -0.3V to (VEXT + 0.3V) TX1, RX1, CTS1, GPIO4, GPIO5, GPIO6, GPIO7..............
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MAX14830 Quad Serial UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.5V, VL = +1.8V, VEXT = +2.8V, TA = +25NC.
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MAX14830 Quad Serial UART with 128-Word FIFOs DC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.5V, VL = +1.8V, VEXT = +2.8V, TA = +25NC.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP RX0, RX1, RX2, RX3, CTS0, CTS1, CTS2, CTS3 INPUTS Input Low Voltage VIL Input High Voltage 0.3 x VEXT 0.
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MAX14830 Quad Serial UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.
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MAX14830 Quad Serial UART with 128-Word FIFOs AC ELECTRICAL CHARACTERISTICS (continued) (VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25NC.) (Notes 2, 3) PARAMETER SYMBOL SCL and SDA I/O Capacitance CI/O Pulse Width of Spike Suppressed tSP CONDITIONS MIN (Note 5) TYP MAX UNITS 10 pF 50 ns SPI BUS: TIMING CHARACTERISTICS (SEE FIGURE 2) tCH+CL 38.
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MAX14830 Quad Serial UART with 128-Word FIFOs Test Circuits/Timing Diagrams START CONDITION (S) REPEATED START CONDITION (Sr) tR STOP CONDITION (P) tF SDA tBUF tHD:STA tHD:DAT tHD:STA tSU:DAT tSU:STO tSU:STA SCL tHIGH tR tF START CONDITION (S) tLOW Figure 1. I2C Timing Diagram CS tCSS tCL tCH tCSH SCLK tDS tDH MOSI tDO MISO Figure 2.
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MAX14830 Quad Serial UART with 128-Word FIFOs Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) GPIO_ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT (PUSH-PULL) 140 120 VEXT = 3.3V 50 ISINK (mA) VEXT = 2.5V 40 30 MAX14830 toc02 60 ISOURCE (mA) 160 MAX14830 toc01 70 GPIO_ OUTPUT LOW VOLTAGE vs. SINK CURRENT (PUSH-PULL) VEXT = 1.8V VEXT = 3.3V 100 80 VEXT = 2.5V 60 20 40 10 VEXT = 1.
PAGE 15
MAX14830 Quad Serial UART with 128-Word FIFOs RX1 TX1 GPIO8 GPIO9 GPIO10 RTS2 GPIO11 CTS2 RX2 TX2 TOP VIEW GPIO12 GPIO13 Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 GPIO14 37 24 CTS1 GPIO15 38 23 RTS1 RTS3 39 22 GPIO7 CTS3 40 21 GPIO6 RX3 41 20 GPIO5 19 GPIO4 18 TX0 TX3 42 VEXT 43 XOUT 44 17 RX0 XIN 45 16 CTS0 AGND 46 15 RTS0 14 GPIO3 13 GPIO2 9 10 11 12 GPIO1 8 GPIO0 7 DGND SCLK/SCL 6 VL MISO/SDA *CONNECT EP TO AGND.
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MAX14830 Quad Serial UART with 128-Word FIFOs Pin Description (continued) PIN NAME FUNCTION 9 VL Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/ A1, CS/A0, SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND. 10 DGND Digital Ground 11 GPIO0 General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source.
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MAX14830 Quad Serial UART with 128-Word FIFOs Pin Description (continued) PIN NAME FUNCTION 28 GPIO9 General-Purpose Input/Output 9. GPIO9 is user-programmable as an input or output (push-pull or open drain) or external event interrupt source. GPIO9 has a weak pulldown resistor to ground. GPIO9 is the TIMER output when bit 7 of the TIMER2 register is set to 1. 29 GPIO10 General-Purpose Input/Output 10.
PAGE 18
MAX14830 Quad Serial UART with 128-Word FIFOs Detailed Description The MAX14830 quad UART bridges an SPI/MICROWIRE™ or I2C microprocessor bus to an asynchronous interface like RS-485, RS-232, or IrDA. The MAX14830 contains advanced UARTs and baud-rate generators with a synchronous serial-data interface and an interrupt generator. The MAX14830 is configured by writing an 8-bit word to the configuration registers through either SPI or I2C.
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MAX14830 Quad Serial UART with 128-Word FIFOs LSB RECEIVED DATA START MSB D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP MID BIT SAMPLING Figure 4. Receive Data Format RECEIVED DATA RECEIVER LSR[1] ISR[3] OVERRUN WORD TRIGGER The contents of the TxFIFO and RxFIFOs are both cleared through MODE2[1]: FIFORst. To halt transmission, set MODE1[1]: TxDisabl to 1. After MODE1[1] is set, the transmitter completes transmission of the current character and then ceases transmission.
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MAX14830 Quad Serial UART with 128-Word FIFOs The receiver can be turned off through MODE1[0]: RxDisabl. When this bit is set to 1, the MAX14830 turns the receiver off immediately following the current word and does not receive any further data. The RX_ input logic can be inverted through IrDA[4]: RxInv. Line Noise Indication When operating in standard or 2x (i.e. not 4x) rate mode, the MAX14830 checks that the binary logic level of the three samples per received bit are identical.
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MAX14830 Quad Serial UART with 128-Word FIFOs Fractional Baud-Rate Generators The internal fractional baud-rate generator provides a high degree of flexibility and high resolution in baudrate programming. The baud-rate generator has a 16-bit integer divisor and a 4-bit word for the fractional divisor. The fractional baud-rate generator can be used with the external crystal or clock source.
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MAX14830 Quad Serial UART with 128-Word FIFOs UART_ FRACTIONAL RATE GENERATOR fREF TmrtoGPIO DIVIDE-BY-1024 TIMERx GPIO_ GPIO_ Figure 9. GPIO_ Clock Pulse Generator Low-Frequency Timer The general-purpose timer can be used to generate a low-frequency clock at a GPIO output and can, for example, be used to drive external LEDs. The low-frequency clock is a divided replica of a given UART baud-rate clock.
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MAX14830 Quad Serial UART with 128-Word FIFOs This occurs as soon as data is present in the Transmit FIFO. Auto transceiver direction control is enabled through MODE1[4]: TrnscvCtrl. Figure 10 shows a typical MAX14830 connection in a RS-485 application. The RTS_ output can be set high in advance of TX_ transmission by a programmable time period called the setup time (Figure 11). The setup time is programmed through HDplxDelay[7:4].
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MAX14830 Quad Serial UART with 128-Word FIFOs SCLK UNCERTAINTY INTERVAL TX_ tTRIG_MIN tTRIG_MAX Figure 12. Single Transmitter Trigger Accuracy Trigger Accuracy The delay between the time when the MAX14830 receives a trigger command and the time when the associated transmitter starts transmission is made up of a fixed, deterministic portion and a variable, random component. Both portions of the delay are dependent on the UART’s clock and baud rates.
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MAX14830 Quad Serial UART with 128-Word FIFOs SCLK tTX0_MIN TX0 tTX0_MAX TX1 tTX1_MIN tTX1_MAX tTRIGSKEW Figure 13. Multiple Transmitter Synchronization Accuracy STOP BIT TX_ HOLD DELAY DI TO RO PROPAGATION DELAY RX_ RTS_ Figure 14.
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MAX14830 Quad Serial UART with 128-Word FIFOs Echo suppression can operate simultaneously with auto transceiver direction control (Figure 15). Auto Hardware Flow Control The MAX14830 is capable of automatic hardware (RTS and CTS) flow control without the need for host processor intervention. When AutoRTS control is enabled, the MAX14830 automatically controls the RTS handshake without the need for host processor intervention.
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MAX14830 Quad Serial UART with 128-Word FIFOs Transmitter Flow Control When auto transmitter control (FlowCtrl[5:4]) is enabled, the receiver compares all received words with the XOFF and XON characters. If an XOFF character is received, the MAX14830 halts its transmitter from sending further data. The receiver is not affected and continues reception. Upon receiving XON, the transmitter then restarts sending data.
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MAX14830 Quad Serial UART with 128-Word FIFOs register to determine which UART is the source of the interrupt. The interrupt sources are divided into top-level and low-level interrupts. The top-level interrupts typically occur more often and can be read out directly through the ISR. The low-level interrupts typically occur less often and their specific source can be read out through the LSR, STSInt, or SpclChar registers.
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MAX14830 Quad Serial UART with 128-Word FIFOs Register Map (continued) REGISTER ADDR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 GPIOs GPIOConfg¥ 0x18 GP3OD GP2OD GP1OD GP0OD GP3Out GP2Out GP1Out GP0Out GPIOData¥ 0x19 GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat CLOCK CONFIGURATION PLLConfig*‡ 0x1A PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0 BRGConfig 0x1B — CLKDisabl 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0 DIVLSB
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MAX14830 Quad Serial UART with 128-Word FIFOs Detailed Register Description The MAX14830 has registers that are 8 bits wide. RHR—Receive Hold Register ADDRESS: MODE: 0x00 R BIT 7 6 5 4 3 2 1 0 NAME RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0 RESET X X X X X X X X Bits 7–0: RData[n] The RHR is the bottom of the Receive FIFO and is the register used for reading data out of the Receive FIFO. It contains the oldest (first received) character in the Receive FIFO.
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MAX14830 Quad Serial UART with 128-Word FIFOs IRQEn—IRQ Enable Register ADDRESS: MODE: 0x01 R/W BIT 7 6 5 4 3 2 1 0 NAME CTSIEn RFifoEmtyIEn TFifoEmtyIEn TFifoTrgIEn RFifoTrgIEn STSIEn SpclChrIEn LSRErrIEn RESET 0 0 0 0 0 0 0 0 The IRQEn register is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled to generate an IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or behavior.
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MAX14830 Quad Serial UART with 128-Word FIFOs ISR—Interrupt Status Register ADDRESS: MODE: 0x02 COR BIT 7 6 5 4 3 2 1 0 NAME CTSInt RFifoEmptyInt TFifoEmptyInt TFifoTrigInt RFifoTrigInt STSInt SpCharInt LSRErrInt RESET 0 1 1 0 0 0 0 0 The Interrupt Status Register provides an overview of all interrupts generated in the MAX14830. These interrupts are cleared upon reading the ISR. When the MAX14830 is operated in polled mode, the ISR can be polled to establish the UART’s status.
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MAX14830 Quad Serial UART with 128-Word FIFOs LSRIntEn—Line Status Interrupt Enable Register ADDRESS: MODE: 0x03 R/W BIT 7 6 5 4 3 2 1 0 NAME — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn RESET 0 0 0 0 0 0 0 0 The LSR Interrupt Enable register allows routing of LSR interrupt bits to the ISR[0]. Bits 7, 6: No Function Bit 5: NoiseIntEn Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0].
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MAX14830 Quad Serial UART with 128-Word FIFOs LSR—Line Status Register ADDRESS: MODE: 0x04 R BIT NAME RESET 7 6 5 4 3 2 1 0 CTSbit X — RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout 0 0 0 0 0 0 0 The Line Status Register shows all errors related to the word in the RxFIFO most recently read out of the RHR. The LSR bits are not cleared upon a read; these bits stay set until the next character without errors is read out of the RHR.
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MAX14830 Quad Serial UART with 128-Word FIFOs Bit 0: RTimeout The RTimeout bit indicates that stale data is present in the Receive FIFO. RTimeout is set when the youngest character resides in the RxFIFO for a period longer than the time programmed into the RxTimeOut register. The timeout counter restarts when at least one character is read out of the RxFIFO or a new character is received by the RxFIFO. If the value in RxTimeOut is zero, LSR[0]: RTimeout is disabled.
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MAX14830 Quad Serial UART with 128-Word FIFOs SpclCharInt—Special Character Interrupt Register ADDRESS: MODE: 0x06 COR BIT 7 6 5 4 3 2 1 0 NAME — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int RESET 0 0 0 0 0 0 0 0 Bits 7, 6: No Function Bit 5: MultiDropInt The MultiDropInt interrupt is set when the MAX14830 receives an address character in 9-bit multidrop mode (MODE2[6] = 1). This bit is cleared when SpclCharInt is read.
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MAX14830 Quad Serial UART with 128-Word FIFOs STSIntEn—STS Interrupt Enable Register ADDRESS: MODE: 0x07 R/W BIT 7 6 5 4 3 2 1 0 NAME — — ClockRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn RESET 0 0 0 0 0 0 0 0 Bits 7, 6: No Function Bit 5: ClkRdyIntEn Set the ClkRdyIntEn bit high to route the ClockReady status bit to the ISR[2]: STSInt bit. If set low, the STSIntEn[5] masks the ISR[2] bit from the ClockReady status.
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MAX14830 Quad Serial UART with 128-Word FIFOs STSInt—Status Interrupt Register ADDRESS: MODE: 0x08 R/COR BIT 7 6 5 4 3 2 1 0 NAME — — ClockReady — GPI3Int GPI2Int GPI1Int GPI0Int RESET 0 0 0 0 0 0 0 0 Bits 7, 6: No Function Bit 5: ClockReady The ClockReady bit is set high when the clock, the divider, and PLL have settled and the MAX14830 is ready for data communication. The ClockReady bit only works with the crystal oscillator.
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MAX14830 Quad Serial UART with 128-Word FIFOs MODE1 Register ADDRESS: MODE: 0x09 R/W BIT 7 6 5 4 3 2 1 0 NAME IRQSel — — TrnscvCtrl RTSHiZ TxHiZ TxDisabl RxDisabl RESET 0 0 0 0 0 0 0 0 Bit 7: IRQSel Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware or software (MODE2[0]) reset, the IRQSel bit is set low and, after a short delay, the IRQ output signals the end of the power-up sequence.
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MAX14830 Quad Serial UART with 128-Word FIFOs MODE2 Register ADDRESS: MODE: 0x0A R/W BIT 7 6 5 4 3 2 1 0 NAME EchoSuprs MultiDrop Loopback SpecialChr RxEmtyInv RxTrigInv FIFORst RST RESET 0 0 0 0 0 0 0 0 Bit 7: EchoSuprs Set the EchoSuprs bit high so that the receiver (RX_) gates any data it receives when its transmitter is busy transmitting. In half-duplex communication (like IrDA and RS-485) this allows blocking of the locally echoed data.
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MAX14830 Quad Serial UART with 128-Word FIFOs Bit 0: RST Set the RST bit high to reset the selected UART in the MAX14830. The SPI/I2C bus stays active during this reset and communication with the MAX14830 is possible. All register bits in the selected UART are reset to their reset state and the FIFOs are cleared during a reset. The global registers are not reset when the RST bit for a given UART is set. Once set high, the RST bit must be cleared by writing a 0 to RST.
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MAX14830 Quad Serial UART with 128-Word FIFOs RxTimeOut—Receiver Timeout Register ADDRESS: MODE: 0x0C R/W BIT 7 6 5 4 3 2 1 0 NAME TimOut7 TimOut6 TimOut5 TimOut4 TimOut3 TimOut2 TimOut1 TimOut0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TimOut[n] The receive data timeout bits allow programming a time delay after the last (newest) character in the Receive FIFO was received until a receive data timeout LSR[0] interrupt is generated.
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MAX14830 Quad Serial UART with 128-Word FIFOs IrDA Register ADDRESS: MODE: 0x0E R/W BIT 7 6 5 4 3 2 1 0 NAME — — TxInv RxInv MIR RTSInvert SIR IrDAEn RESET 0 0 0 0 0 0 0 0 The IrDA register allows selection of IrDA SIR- and MIR-compliant pulse shaping at the TX_ and RX_ interfaces. It also allows inversion of the TX_ and RX_ logic, independently of whether IrDA is enabled or not. Bits 7, 6: No Function Bit 5: TxInv Set the TxInv bit high to invert the logic at the TX_ output.
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MAX14830 Quad Serial UART with 128-Word FIFOs FlowLvl—Flow Level Register ADDRESS: MODE: 0x0F R/W BIT 7 6 5 4 3 2 1 0 NAME Resume3 Resume2 Resume1 Resume0 Halt3 Halt2 Halt1 Halt0 RESET 0 0 0 0 0 0 0 0 FlowLvl is used for selecting the RxFIFO threshold levels used for software (XON/XOFF) and hardware (RTS/CTS) flow control. Bits 7–4: Resume[n] Resume[n] bits set the Transmit FIFO threshold at which an XON is automatically sent or RTS_ is automatically set low.
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MAX14830 Quad Serial UART with 128-Word FIFOs TxFIFOLvl—Transmit FIFO Level Register ADDRESS: MODE: 0x11 R BIT 7 6 5 4 3 2 1 0 NAME TxFL7 TxFL6 TxFL5 TxFL4 TxFL3 TxFL2 TxFL1 TxFL0 RESET 0 0 0 0 0 0 0 0 Bits 7–0: TxFL[n] The TxFIFOLvl register represents the current number of words in the Transmit FIFO.
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MAX14830 Quad Serial UART with 128-Word FIFOs Table 4. SwFlow_ Truth Table SwFlow3 SwFlow2 RECEIVER FLOW CONTROL SwFlow1 SwFlow0 TRANSMITTER FLOW CONTROL/SPECIAL CHARACTER DETECTION DESCRIPTION 0 0 0 0 No flow control. No character detection. 0 0 X X No receiver flow control. 1 0 X X Transmitter generates XON1, XOFF1. 0 1 X X Transmitter generates XON2, XOFF2. 1 1 X X Transmitter generates XON1, XON2, XOFF1, and XOFF2. X X 0 0 No transmitter flow control.
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MAX14830 Quad Serial UART with 128-Word FIFOs XON1 Register ADDRESS: MODE: 0x14 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XON1 and XON2 register contents define the XON characters used for automatic XON/XOFF flow control and/or the special characters used for special character detection. See details in the FlowCtrl register description.
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MAX14830 Quad Serial UART with 128-Word FIFOs XOFF1 Register ADDRESS: MODE: 0x16 R/W BIT 7 6 5 4 3 2 1 0 NAME Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RESET 0 0 0 0 0 0 0 0 The XOFF1 and XOFF2 register contents define the XOFF characters for automatic XON/XOFF flow control and/or the special characters used in special character detection. See details in the FlowCtrl register description.
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MAX14830 Quad Serial UART with 128-Word FIFOs GPIOConfg—GPIO Configuration Register ADDRESS: MODE: 0x18 R/W BIT 7 6 5 4 3 2 1 0 NAME GP3OD GP2OD GP1OD GP0OD GP3Out GP2Out GP1Out GP0Out RESET 0 0 0 0 0 0 0 0 Each UART has four GPIOs that can be configured as inputs or outputs and can be operated in push-pull or open-drain mode. The reference clock must be active for the GPIOs to work.
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MAX14830 Quad Serial UART with 128-Word FIFOs GPIOData—GPIO Data Register ADDRESS: MODE: 0x19 R/W BIT 7 6 5 4 3 2 1 0 NAME GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat RESET 0 0 0 0 0 0 0 0 Bits 7–4: GPI[n]Dat Each UART has four individually assigned GPIO outputs as follows: UART0: GPIO0–GPIO3, UART1: GPIO4–GPIO7, UART2: GPIO8–GPIO11, UART3: GPIO12–GPIO15.
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MAX14830 Quad Serial UART with 128-Word FIFOs PLLConfig—PLL Configuration Register ADDRESS: MODE: 0x1A R/W BIT 7 6 5 4 3 2 1 0 NAME PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0 RESET 0 0 0 0 0 0 0 1 Bits 7, 6: PLLFactor[n] The PLLFactor[n] bits allow programming the PLL multiplication factors. The input and output frequencies of the PLL have to be limited to the ranges shown in Table 7. Enable the PLL through CLKSource[2].
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MAX14830 Quad Serial UART with 128-Word FIFOs BRGConfig—Baud-Rate Generator Configuration Register ADDRESS: MODE: 0x1B R/W BIT 7 6 5 4 3 2 1 0 NAME — CLKDisabl 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0 RESET 0 0 0 0 0 0 0 0 Bit 7: No Function Bit 6: CLKDisabl Set the CLKDisabl bit high to disable internal clocking of the UART. This is useful to achieve fast baud rate reprogramming or to reduce power dissipation when a specific UART channel is not used.
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MAX14830 Quad Serial UART with 128-Word FIFOs CLKSource—Clock Source Register ADDRESS: MODE: 0x1E R/W BIT 7 6 5 4 3 2 1 0 NAME CLKtoRTS — — — PLLBypass PLLEn CrystalEn — RESET 0 0 0 0 1 0 0 0 Bit 7: CLKtoRTS Set the CLKtoRTS bit to 1 to route the baud-rate generator (16x baud rate) output clock to RTS_. The clock frequency is a factor of 16x, 8x, or 4x of the baud rate, depending on the BRGConfig[5:4] settings.
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MAX14830 Quad Serial UART with 128-Word FIFOs GloblComnd—Global Command Register ADDRESS: MODE: 0x1F W BIT 7 6 5 4 3 2 1 0 NAME GlbCom7 GlbCom6 GlbCom5 GlbCom4 GlbCom3 GlbCom2 GlbCom1 GlbCom0 Bits 7–0: GlbCom[n] The GloblComnd register is the only global write register in the MAX14830. Every byte written to GloblComnd is sent simultaneously to all four UARTs. Every byte sent by the SPI/I2C master to location 0x1F is interpreted as a global command by all the four internal UARTs.
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MAX14830 Quad Serial UART with 128-Word FIFOs TxSynch—Transmitter Synchronization Register ADDRESS: MODE: 0x20 R/W BIT 7 6 5 4 3 2 1 0 NAME CLKtoGPIO TxAutoDis TrigDelay SynchEn TrigSel3 TrigSel2 TrigSel1 TrigSel0 RESET 0 0 0 0 0 0 0 0 The TxSynch register is used to configure transmitter synchronization with a global SPI or I2C command. One of 16 trigger commands (Table 5) can be selected to be the synchronization trigger source for every UART.
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MAX14830 Quad Serial UART with 128-Word FIFOs SynchDelay1—Synchronization Delay Register 1 ADDRESS: MODE: 0x21 R/W BIT 7 6 5 4 3 2 1 0 NAME SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0 RESET 0 0 0 0 0 0 0 0 The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an assigned transmitter trigger command and when the UART begins transmission.
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MAX14830 Quad Serial UART with 128-Word FIFOs TIMER2—Timer Register 2 ADDRESS: MODE: 0x24 R/W BIT 7 6 5 4 3 2 1 0 NAME TmrToGPIO Timer14 Timer13 Timer12 Timer11 Timer10 Timer9 Timer8 RESET 0 0 0 0 0 0 0 0 The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output. The low-frequency clock is a divided replica of the fractional divider output. Bit 7: TmrToGPIO Set TmrToGPIO to 1 to enable clock generation at a GPIO output.
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MAX14830 Quad Serial UART with 128-Word FIFOs Table 10. SPI Command Byte Configuration SPI COMMAND BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 W/R U1 U0 A4 A3 A2 A1 A0 A[4:0] = Register Address Table 11. SPI U1, U0 UART Selection U1 U0 UART SELECTED 0 0 UART0 0 1 UART1 1 0 UART2 1 1 UART3 address (U1 and U0) has been properly decoded, the addressed SPI drives the MISO line (Figure 19).
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MAX14830 Quad Serial UART with 128-Word FIFOs CS SCLK MOSI R U1 U0 A4 HiZ MISO A3 A2 A1 A0 IRQ3 IRQ2 IRQ1 IRQ0 X D7 D6 D5 D4 D3 D2 D1 D0 UX = UART ADDRESS AX = REGISTER ADDRESS DX = EIGHT-BIT REGISTER CONTENTS = INSTANT AT WHICH MAX14830 SAMPLES MOSI DATA = INSTANT AT WHICH MAX14830 WRITES MISO DATA Figure 19.
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MAX14830 Quad Serial UART with 128-Word FIFOs S Sr P SCL SDA Figure 21. I2C START, STOP, and Repeated START Conditions Table 12.
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MAX14830 Quad Serial UART with 128-Word FIFOs WRITE SINGLE BYTE S DEVICE SLAVE ADDRESS - W A 8 DATA BITS A FROM MASTER TO STAVE REGISTER ADDRESS A P FROM SLAVE TO MASTER Figure 22. Write Byte Sequence BURST WRITE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - N A FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 23. Burst Write Sequence Bit Transfer One data bit is transferred during each SCL clock cycle.
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MAX14830 Quad Serial UART with 128-Word FIFOs READ SINGLE BYTE S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A Sr DEVICE SLAVE ADDRESS - R A 8 DATA BITS NA FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 24. Read Byte Sequence BURST READ S DEVICE SLAVE ADDRESS - W A REGISTER ADDRESS A Sr DEVICE SLAVE ADDRESS - R A 8 DATA BITS - 1 A 8 DATA BITS - 2 A 8 DATA BITS - 3 A 8 DATA BITS - N NA FROM MASTER TO STAVE P FROM SLAVE TO MASTER Figure 25.
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MAX14830 Quad Serial UART with 128-Word FIFOs Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX14830 generate ACK bits. To generate an ACK, pull SDA low before the rising edge of the ninth clock pulse and keep it low during the high period of the ninth clock pulse (Figure 26). To generate a NACK, leave SDA high before the rising edge of the ninth clock pulse and keep it high for the duration of the ninth clock pulse.
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MAX14830 Quad Serial UART with 128-Word FIFOs 1.8V 3.3V 2.5V VDD VA VL RST MICROCONTROLLER VEXT VCC TX_ DI RX_ RO RTS_ DE MAX3078 SPI/I2C MAX14830 TRANSCEIVER IRQ AGND DGND Figure 28.
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MAX14830 Quad Serial UART with 128-Word FIFOs Typical Operating Circuit MISO MOSI CONTROLLER SCLK CS1 CS2 RST RST MAX14824 CS SCLK MOSI MISO TX0 RX0 RTSO PORT1 RX TXC TXEN ADDR1 VEXT MAX14824 PORT2 TX1 RX1 RTS1 GPIO1 GPIO5 GPIO9 RX TXC TXEN ADDR2 MAX14830 MAX14824 GPIO13 PORT3 TX2 RX2 RTS2 RX TXC TXEN ADDR3 MAX14824 PORT4 XIN XOUT TX3 RX3 RTS3 RX TXC TXEN ADDR4 IO-LINK QUAD MASTER APPLICATION Maxim Integrated 65
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MAX14830 Quad Serial UART with 128-Word FIFOs Typical Operating Circuits (continued) 3.3V 0.1µF 0.1µF VA VEXT VL TX0 SPI/I2C RTS0 MICROCONTROLLER MOSI MOSI TX0 MISO MAX14840 V18 LDOEN MAX14830 SCLK 1µF 0.
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MAX14830 Quad Serial UART with 128-Word FIFOs Chip Information PROCESS: BiCMOS Maxim Integrated Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
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MAX14830 Quad Serial UART with 128-Word FIFOs Revision History REVISION NUMBER REVISION DATE 0 9/10 Initial release 1 12/10 Corrected specifications in the Absolute Maximum Ratings and DC Electrical Characteristics, updated the Register Map, corrected Table 12 DESCRIPTION PAGES CHANGED — 2 9/11 Removed internal oscillator description throughout data sheet; deleted TOCs 1 and 2; corrected Figure 7; changed V18 capacitor to 1FF; corrected I2C burst read sequence; corrected ISR description; added R