Datasheet
56 Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
SynchDelay1—Synchronization Delay Register 1
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelay[n]
SDelay[7:0] are the 8 LSBs of the delay between when the UART receives an assigned transmitter trigger command
and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate). The
maximum delay is 65,535-bit intervals.
For example, given a baud rate of 230.4kbps and a bit time of 4.34Fs, the maximum delay is 284ms.
SynchDelay2—Synchronization Delay Register 2
The SynchDelay1 and SynchDelay2 register contents define the time delay between when the UART receives an
assigned transmitter trigger command and when the UART begins transmission.
Bits 7–0: SDelay[n]
SDelay[15:8] are the 8 MSBs of the delay between when the UART receives an assigned transmitter trigger command
and when the UART begins transmission. The delay is expressed in number of UART bit intervals (1/BaudRate). The
maximum delay is 65,535-bit intervals.
For example, given a baud rate of 230.4kbps and a bit time of 4.34Fs, the maximum delay is 284ms.
TIMER1—Timer Register 1
The TIMER1 and TIMER2 register contents can be used to generate a low-frequency clock signal on a GPIO_ output.
The low-frequency clock is a divided replica of the fractional divider output.
Bits 7–0: Timer[n]
Timer[7:0] are the 8 LSBs of the 15-bit timer divisor. See the TIMER2 register description.
If TIMER1 and TIMER2 are both 0x00, the low-frequency clock is off.
ADDRESS: 0x21
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
SDelay7 SDelay6 SDelay5 SDelay4 SDelay3 SDelay2 SDelay1 SDelay0
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x22
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
SDelay15 SDelay14 SDelay13 SDelay12 SDelay11 SDelay10 SDelay9 SDelay8
RESET
0 0 0 0 0 0 0 0
ADDRESS: 0x23
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME
Timer7 Timer6 Timer5 Timer4 Timer3 Timer2 Timer1 Timer0
RESET
0 0 0 0 0 0 0 0