Datasheet

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General Description

The MAX1492/MAX1494 low-power, 3.5- and 4.5-digit,

analog-to-digital converters (ADCs) with integrated liquid

crystal display (LCD) drivers operate from a single 2.7V

to 5.25V power supply. They include an internal refer-

ence, a high-accuracy on-chip oscillator, and a triplexed

LCD driver. An internal charge pump generates the neg-

ative supply needed to power the integrated input buffer

for single-supply operation. The ADCs are configurable

for either a ±2V or ±200mV input range and outputs its

conversion results to an LCD and/or to a microcontroller

(µC). µC communication is facilitated through an

SPI™-/QSPI™-/MICROWIRE

-compatible serial inter-

face. The MAX1492 is a 3.5-digit (±1999 count) device,

and the MAX1494 is a 4.5-digit (±19,999 count) device.

The MAX1492/MAX1494 do not require external-preci-

sion integrating capacitors, autozero capacitors, crystal

oscillators, charge pumps, or other circuitry required

with dual-slope ADCs (commonly used in panel meter

circuits).

These devices also feature on-chip buffers for the dif-

ferential signal and reference inputs, allowing direct

interface with high-impedance signal sources. In addi-

tion, they use continuous internal-offset calibration and

offer >100dB simultaneous rejection of 50Hz and 60Hz

line noise. Other features include data hold and peak

hold, overrange and underrange detection, and a low-

battery monitor.

The MAX1494 comes in a 32-pin, 7mm x 7mm LQFP

package, and the MAX1492 comes in 28-pin SSOP and

28-pin PDIP packages. All devices in this family operate

over the 0°C to +70°C commercial temperature range.

Applications

Digital Panel Meters

Hand-Held Meters

Digital Voltmeters

Digital Multimeters

Features

o High Resolution

MAX1494: 4.5 Digits (±19,999 Count)

MAX1492: 3.5 Digits (±1999 Count)

o Sigma-Delta ADC Architecture

No Integrating Capacitors Required

No Autozeroing Capacitors Required

>100dB of Simultaneous 50Hz and 60Hz

Rejection

o Operate from a Single 2.7V or 5.25V Supply

o Selectable Input Range of ±200mV or ±2V

o Selectable Voltage Reference: Internal 2.048V

or External

o Internal High-Accuracy Oscillator Needs No

External Components

o Automatic Offset Calibration

o Low Power

Maximum 960µA Operating Current

Maximum 400µA Shutdown Current

o Small 32-Pin 7mm x 7mm LQFP Package

(4.5 Digits), 28-Pin SSOP Package (3.5 Digits)

o Triplexed LCD Driver

o SPI-/QSPI-/MICROWIRE-Compatible Serial

Interface

o Evaluation Kit Available (Order MAX1494EVKIT)

MAX1492/MAX1494

3.5- and 4.5-Digit, Single-Chip ADCs

with LCD Drivers

________________________________________________________________

Maxim Integrated Products

Ordering Information/

Selector Guide

19-2959; Rev 4; 7/10

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART

TEMP

RANGE

PIN-

PACKAGE

RESOLUTION

(DIGITS)

MAX1492CAI+ 0°C to +70°C 28 SSOP 3.5

MAX1492CNI+ 0°C to +70°C 28 PDIP 3.5

MAX1494CCJ+ 0°C to +70°C 32 LQFP 4.5

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

Denotes a lead(Pb)-free/RoHS-compliant package.

Pin Configurations appear at end of data sheet.

Summary of content (34 pages)

PAGE 1
9-2959; Rev 4; 7/10 KIT ATION EVALU E L B A IL AVA 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Features The MAX1492/MAX1494 low-power, 3.5- and 4.5-digit, analog-to-digital converters (ADCs) with integrated liquid crystal display (LCD) drivers operate from a single 2.7V to 5.25V power supply. They include an internal reference, a high-accuracy on-chip oscillator, and a triplexed LCD driver.
PAGE 2
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers ABSOLUTE MAXIMUM RATINGS AVDD to GND...........................................................-0.3V to +6V DVDD to GND...........................................................-0.3V to +6V AIN+, AIN- to GND ...............................VNEG to +(AVDD + 0.3V) REF+, REF- to GND ..............................VNEG to +(AVDD + 0.3V) LOWBATT to GND...................................-0.3V to (AVDD + 0.
PAGE 3
.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers (VAVDD = VDVDD = 2.7V to 5.25V, VGND = 0V, VREF+ - VREF- = 2.048V (external reference). Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Normal-Mode 50Hz and 60Hz Rejection (Simultaneously) CONDITIONS MIN TYP Internal clock mode, 50Hz and 60Hz ±2% 100 External clock mode, 50Hz and 60Hz ±2%, fCLK = 4.
PAGE 4
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 2.7V to 5.25V, VGND = 0V, VREF+ - VREF- = 2.048V (external reference). Internal clock mode, unless otherwise noted. All specifications are at TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -2.60 -2.42 -2.30 V +10 µA 0.3 x VDVDD V CHARGE PUMP (CNEG = 0.
PAGE 5
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers (VAVDD = VDVDD = 2.7V to 5.25V, VGND = 0V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SCLK Operating Frequency SYMBOL CONDITIONS MIN TYP MAX UNITS 4.
PAGE 6
Typical Operating Characteristics (VAVDD = VDVDD = 5V, VGND = 0V, external reference mode, REF+ = 2.048V, REF- = GND, RANGE bit = 1, internal clock mode, TA = +25°C, unless otherwise noted.) MAX1494 (±200mV INPUT RANGE) INL vs. OUTPUT CODE -0.5 -1.0 -20,000 -10,000 0 10,000 SUPPLY CURRENT vs. SUPPLY VOLTAGE OUTPUT CODE NOISE (LSB) MAX1494 OFFSET ERROR vs. SUPPLY VOLTAGE MAX1494 OFFSET ERROR vs. TEMPERATURE 300 DIGITAL SUPPLY MAX1492/94 toc05 0.04 -0.01 -0.06 3.25 3.75 4.25 4.75 0.1 3.
PAGE 7
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers 2.047 2.046 ANALOG SUPPLY 500 400 300 DIGITAL SUPPLY 200 2.045 3.25 3.75 4.25 4.75 5.25 10 20 30 40 50 60 10 20 30 40 50 60 TEMPERATURE (°C) CHARGE-PUMP OUTPUT VOLTAGE vs. ANALOG SUPPLY VOLTAGE VNEG STARTUP SCOPE SHOT MAX1492/94 toc14 -2.42 VNEG VOLTAGE (V) 200 0 70 TEMPERATURE (°C) -2.40 MAX1492/94 toc13 SUPPLY CURRENT (µA) ANALOG SUPPLY 100 0 0 SHUTDOWN SUPPLY CURRENT vs.
PAGE 8
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers MAX1492/MAX1494 Pin Description PIN MAX1492 8 MAX1494 NAME FUNCTION 1 30 CLK External Clock Input. When the EXTCLK bit in the control register is set, CLK is the master clock input for the modulator and the filter (frequency = 4.9152MHz). When the EXTCLK bit in the control register is reset, the internal clock is used. Connect CLK to GND or DVDD when the internal oscillator is used. 2 31 DVDD Digital Power Input. Connect DVDD to a 2.7V to 5.
PAGE 9
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers PIN NAME FUNCTION MAX1492 MAX1494 24 21 SEG10 LCD Segment 10 Driver 25 25 BP3 LCD Backplane 3 Driver 26 26 BP2 LCD Backplane 2 Driver 27 27 BP1 LCD Backplane 1 Driver 28 29 VNEG — 22 SEG11 LCD Segment 11 Driver — 23 SEG12 LCD Segment 12 Driver — 24 SEG13 LCD Segment 13 Driver — 28 VDISP Temperature-Compensation Voltage Input for LCD. If not using temperature compensation, connect VDISP to GND.
PAGE 10
Detailed Description The MAX1492/MAX1494 low-power, highly integrated ADCs with LCD drivers convert a ±2V differential input voltage (one count is equal to 100µV for the MAX1494 and 1mV for the MAX1492) with a sigma-delta ADC and output the result to an LCD or µC. An additional ±200mV input range (one count is equal to 10µV for the MAX1494 and 100µV for the MAX1492) is available to measure small signals with increased resolution. The devices operate from a single 2.7V to 5.25V power supply and offer 3.
PAGE 11
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers X Y Z For large step changes at the input, allow a settling time of 800ms before valid data is read. Clock Modes Configure the MAX1492/MAX1494 to use either the internal oscillator or an externally applied clock to drive the modulator and filter. Set the EXTCLK bit in the control register to 0 to put the device in internal clock mode. Set the EXTCLK bit high to put the device in external clock mode.
PAGE 12
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers HOLD PEAK LOW BATT BP1 BP2 BP3 Figure 4. Backplane Connection for the MAX1494 (4.5 Digits) SEG13: PEAK, HOLD, N.C. HOLD PEAK LOW BATT SEG12: F4, E4, DP4 SEG11: A4, G4, D4 SEG2: A1, G1, D1 ANNUNCIATOR SEG1: B1, C1, N.C. SEG3: F1, E1, DP1 SEG10: B4, C4, BC5 SEG4: B2, C2, LOWBATT SEG9: F3, E3, DP3 SEG8: A3, G3, D3 SEG5: A2, G2, D2 SEG6: F2, E2, DP2 SEG7: B3, C3, MINUS Figure 5. Segment Connection for the MAX1494 (4.
PAGE 13
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers PEAK MAX1492/MAX1494 HOLD LOW BATT BP1 BP2 BP3 Figure 6. Backplane Connection for the MAX1492 (3.5 Digits) SEG10: PEAK, HOLD, BC4 HOLD PEAK LOW BATT SEG2: A1, G1, D1 ANNUNCIATOR SEG1: B1, C1, N.C. SEG3: F1, E1, DP1 SEG4: A2, G2, LOWBATT SEG9: F3, E3, DP3 SEG5: A2, G2, D2 SEG8: A3, G3, D3 SEG6: F2, E2, DP2 SEG7: B3, C3, MINUS Figure 7. Segment Connection for the MAX1492 (3.5 Digits) thus the contrast of the segment.
PAGE 14
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Table 2. Decimal-Point Control Table (MAX1494) DP_EN DPSET1 DPSET2 DISPLAY OUTPUT ZERO INPUT READING 0 0 0 18888 0 0 0 1 18888 0 0 1 0 18888 0 0 1 1 18888 0 1 0 0 1 8 8 8.8 0.0 1 0 1 1 8 8.8 8 0.00 1 1 0 1 8.8 8 8 0.000 1 1 1 1.8 8 8 8 0.0000 Table 3. Decimal-Point Control Table (MAX1492) DP_EN DPSET1 DPSET2 DISPLAY OUTPUT ZERO INPUT READING X 0 0 1 8 8.8 0.0 X 0 1 1 8.8 8 0.
PAGE 15
3.5- and 4.
PAGE 16
MAX1492/MAX1494 3.5- and 4.
PAGE 17
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers φ2 φ3 φ1' φ2' MAX1492/MAX1494 φ1 φ3' VLCD ALL OFF 0 VRMS = VLCD/3 OFF -VP VP a ON g, d OFF 0 VRMS = VLCD/3 OFF -VP VP a, g ON d OFF 0 VRMS = 1.92VLCD/3 ON -VP VP ALL ON 0 VRMS = 1.92VLCD/3 ON -VP VG = VY - VBP2 (DIFFERENCE BETWEEN SEGMENT LINE Y AND BP2 VOLTAGE) VOLTAGE CONTRAST RATIO = VRMSON / VRMSOFF = 1.
PAGE 18
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers 100 90 Ø = -10° 80 Ø = +10° CONTRAST (%) 70 Ø = -30° 60 Ø = 0° 50 40 30 VOFF = 1.1VRMS 20 VON = 2.1VRMS 10 TA = +25°C 0 0 1 2 3 4 5 APPLIED VOLTAGE (VRMS) Ø+ Ø- Figure 12. Contrast vs.
PAGE 19
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers MAX1492/MAX1494 CS tCSS tCSH tCSH tCH tCL SCLK tDS tDH DIN tDV tDO tTR DOUT Figure 13. Detailed Timing Diagram CS SCLK 1 DIN 0 RS4 RS3 RS2 RS1 RS0 x D15 D14 D13 D12 D11 D10 CONTROL BYTE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE DOUT Figure 14. Serial-Interface 16-Bit Write Timing Diagram CS SCLK DIN 1 0 RS4 RS3 RS2 RS1 RS0 x D7 D6 CONTROL BYTE D5 D4 D3 D2 D1 D0 DATA BYTE DOUT Figure 15.
PAGE 20
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers CS SCLK DIN 1 1 RS4 RS3 RS2 RS1 RS0 x DATA BYTE CONTROL BYTE D15 D14 D13 D12 D11 D10 D9 DOUT D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 16. Serial-Interface 16-Bit Read Timing Diagram CS SCLK 1 DIN 1 RS4 RS3 RS2 RS1 RS0 x DATA BYTE CONTROL BYTE D7 DOUT D6 D5 D4 D3 D2 D1 D0 Figure 17. Serial-Interface 8-Bit Read Timing Diagram VDVDD VDVDD 6kΩ DOUT 6kΩ CLOAD 50pF DOUT GND A) VOH TO HIGH-Z Figure 18.
PAGE 21
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Serial Interface The SPI/QSPI/MICROWIRE serial interface consists of a chip select (CS), a serial clock (SCLK), a data in (DIN), a data out (DOUT), and an asynchronous EOC output. EOC provides an asynchronous end-of-conversion signal with a period of 200ms (fCLK = 4.9152MHz or internal clock mode). The MAX1492 updates the data register when EOC goes high. Data is valid in the ADC result registers when EOC returns low.
PAGE 22
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Command Byte (Write Only): MSB LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 START (1) R/W RS4 RS3 RS2 RS1 RS0 X START: (R/W): Start Bit. The first 1 clocked into the MAX1492/MAX1494 is the first bit of the command byte. Read/Write. Set this bit to 1 to read from the specified register. Set this bit to 0 to write to the selected register. Note that certain registers are read-only.
PAGE 23
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers EXTCLK: INTREF: DP_EN: DPSET[2:1]: HOLD: PEAK: PD_ANA: PD_DIG: (Default = 0) Display Select Bit. The SPI/ADC bit controls selection of the data fed into the LCD data register. A 1 in this location selects SPI/QSPI/ MICROWIRE data (the user writes this data to the LCD data register). A 0 in this location selects the ADC result register data, unless hold or peak functions are active (Table 6). (Default = 0) External Clock Select Bit.
PAGE 24
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Table 6. LCD Priority Table SEG_SEL SPI/ADC HOLD PEAK 1 X X X LCD Segment Registers DISPLAYS VALUES FROM 0 1 X X LCD Display Register (User Written) 0 0 1 X LCD Display Register 0 0 0 1 Peak Register 0 0 0 0 ADC Result Register X = Don’t care.
PAGE 25
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers E1: F1: D1: G1: A1: C1: B1: Segment DP Driver Bit of Digit 1. The default value turns on the LCD segment. Segment e Driver Bit of Digit 1. The default value turns on the LCD segment. Segment f Driver Bit of Digit 1. The default value turns on the LCD segment. Segment d Driver Bit of Digit 1. The default value turns on the LCD segment. ANN: Segment g Driver Bit of Digit 1. The default value turns on the LCD segment. Segment a Driver Bit of Digit 1.
PAGE 26
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers LCD Segment-Display Register 3 (Read/Write): MSB LSB PEAK HOLD BC_ B4 C4 A4 G4 D4 Default values: 00h The LCD segment-display register 3 is an 8-bit read/write register. When the SEG_SEL bit (in the control register) is set to 1, the MAX1492/MAX1494 provide direct access to individual LCD segments. The bits in the LCD segment-display register determine if a segment is on or off.
PAGE 27
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers LSB (MAX1492) MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 LSB (MAX1494) D3 D2 D1 D0 Default values: 0000h The LCD data register is a 16-bit read/write register. This register updates from the ADC result register 1, the PEAK register, or from the serial interface by selecting SPI/ADC bit, PEAK bit, and HOLD bit in the control register (Table 6). The data is represented in two’s complement format.
PAGE 28
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Power-On Reset Strain Gauge Measurement At power-up, the serial interface, LCD driver, digital filter, and modulator circuits reset. The registers return to their default values. Allow time for the reference to settle before starting calibration. Connect the differential inputs of the MAX1492/ MAX1494 to the bridge network of the strain gauge.
PAGE 29
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Avoid running digital lines under the device because they can couple noise onto the device. Run the analog ground plane under the MAX1492/MAX1494 to minimize coupling of digital noise. Make the power-supply lines to the MAX1492/MAX1494 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line.
PAGE 30
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers ANALOG SUPPLY TEMP SENSOR FERRITE BEAD 0.1µF 4.7µF 0.1µF 4.7µF AVDD DVDD MAX1492 MAX1494 THERMOCOUPLE JUNCTION REF+ 0.1µF AIN+ RREF REF- SCLK AIN+ +2.048V DIN AIN- DUMMY GAUGE 0.1µF +5V R 0.1µF µC AIN- 0.1µF ACTIVE GAUGE SPI MAX1492 MAX1494 DOUT 0.1µF REF+ MAX6062 REF- CS R EOC GND GND 0.47µF Figure 21. Thermocouple Application with MAX1492/MAX1494 Figure 20.
PAGE 31
3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers 4–20mA R 1---- >4E1Fh 19,999 4E1Fh 2 1 0002h 0 0000h -0 FFFFh -1 FFFEh -2 FFFDh -19,999 B1E0h -1 - - - -
PAGE 32
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers ADC RESULT LCD 1--- >7CFh 1999 7CFh 2 1 002h 0 000h -0 FFFh -1 FFEh -2 FFDh -1999 830h -1 - - - <830h 001h -2V -1mV 0 1mV +2V ANALOG INPUT VOLTAGE Figure 27. MAX1492 Transfer Function ±2V Range Typical Operating Circuit HOLD LOW BATTERY SEG1–SEG13 (SEG1–SEG10) AIN+ VIN PEAK BACKPLANE CONNECTIONS AIN0.1µF CLK 0.1µF SCLK 4.7µF CS MAX1494 (MAX1492) DVDD DIN 0.1µF DOUT EOC AVDD 0.1µF RHI LISO 2.
PAGE 33
3.5- and 4.
PAGE 34
MAX1492/MAX1494 3.5- and 4.5-Digit, Single-Chip ADCs with LCD Drivers Revision History REVISION NUMBER REVISION DATE 4 7/10 DESCRIPTION Added lead-free information to Ordering Information/Selector Guide and updated various items to match current style PAGES CHANGED 1–34 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.