EVALUATION KIT AVAILABLE MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers General Description The MAX16065/MAX16066 flash-configurable system managers monitor and sequence multiple system voltages. The MAX16065/MAX16066 can also accurately monitor (±2.5%) one current channel using a dedicated high-side current-sense amplifier. The MAX16065 manages up to twelve system voltages simultaneously, and the MAX16066 manages up to eight supply voltages.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ABSOLUTE MAXIMUM RATINGS VCC, CSP, CSM to GND.........................................-0.3V to +15V CSP to CSM...........................................................-0.7V to +0.7V MON_, GPIO_, SCL, SDA, A0, RESET, EN_OUT9–EN_OUT12 to GND (programmed as open-drain outputs).........-0.3V to +6V EN, TCK, TMS, TDI to GND.....................................-0.3V to +4V DBP, ABP to GND.......-0.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Bits LSB ADC DC ACCURACY Resolution Gain Error ADCGAIN Offset Error ADCOFF 10 0.35 0.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS OUTPUTS (EN_OUT_, RESET, GPIO_) ISINK = 2mA 0.4 ISINK = 10mA, GPIO_ only 0.7 VCC = 1.2V, ISINK = 100μA (RESET only) 0.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at VABP = VDBP = VCC = 3.3V, TA = +25NC.) (Note 1) PARAMETER SYMBOL Output Fall Time tOF Data Hold Time tHD:DAT Pulse Width of Spike Suppressed CONDITIONS MIN TYP CBUS = 10pF to 400pF From 50% SCL falling to SDA change 0.3 tSP MAX UNITS 250 ns 0.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SDA tSU:DAT tHD:DAT tLOW tBUF tSU:STA tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION Figure 1. SMBus Timing Diagram t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO Figure 2.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Typical Operating Characteristics (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE TA = -40NC ABP AND DBP REGULATORS ACTIVE 2 FOR LOW-VOLTAGE APPLICATIONS VCC < 3.6V CONNECT ABP AND DBP TO VCC 1 0 2 4 6 8 10 0.6 0.4 0.2 MAX16065 toc03 1.002 1.000 0.998 0.996 0.994 0.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Typical Operating Characteristics (continued) (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) 0.8 0.6 0.6 0.4 3.0 0.2 0.2 GPIO_ 2.8 EN_OUT_ 0 -0.2 0 -0.2 2.7 -0.4 -0.4 2.6 -0.6 -0.6 -0.8 -0.8 RESET -1.0 2.4 1000 -1.0 0 1500 128 256 384 512 640 768 896 1024 0 CURRENT-SENSE TRANSIENT DURATION vs. CSP-CSM OVERDRIVE 1.03 MAX16065 toc14 1.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Pin Description PIN NAME FUNCTION MAX16065 MAX16066 1–6, 43–46 40, 1–5, 36–39 MON1– MON10 Monitor Voltage Inputs. Set monitor voltage range through configuration registers. Measured value written to ADC register can be read back through the SMBus or JTAG interface. 47, 48 — MON11, MON12 Monitor Voltage Inputs. Set monitor voltage range through configuration registers.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Functional Diagram ABP VCC DBP OVERC RESET MAX16065 RESET ANY_FAULT FAULT1 DECODE LOGIC FAULT2 MR C O N T R O L MARGIN WATCHDOG TIMER EN WDI WDO GPIO1–GPIO8 PRIMARY SEQUENCE BLOCK 1.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Detailed Description The MAX16065 manages up to twelve system power supplies and the MAX16066 can manage up to eight system power supplies. After boot-up, if EN is high and the software enable bit is set to ‘1,’ a power-up sequence begins based on the configuration stored in flash and the EN_OUT_s are controlled accordingly.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 1.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers of the EN comparator output or the software enable bit. If operating in latch-on fault mode, toggle EN or toggle the Software Enable bit to clear the latch condition and restart the device once the fault condition has been removed. To initiate secondary sequencing and monitoring set the software enable r73h[1] bit to 1.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 4. Power-Up/Power-Down Slot Delays CODE VALUE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 25Fs 500Fs 1ms 2ms 3ms 4ms 6ms 8ms 10ms 12ms 1010 1011 25ms 100ms 1100 1101 200ms 400ms 1110 1111 800ms 1.6s sequence delay is then counted before moving to the next slot. Slot 0 does not monitor any MON_ input and does not control any EN_OUT_.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SLOT 0 SLOT 1 SLOT 2 (PRIMARY SEQUENCE) tFAULT EN_OUT1 SLOT0 DELAY FINAL SLOT SLOT1-SLOT0 DELAY OV BOTH ARE ASSIGNED TO SLOT 1 MON4 UV EN_OUT2 UV/OV MONITORING BEGINS WHEN MON4 REACHES UV THRESHOLD MON4 MUST REACH UV THRESHOLD BY THIS TIME BOTH ARE ASSIGNED TO SLOT 2 RESET TIMEOUT MON3 MON5 RESET EN Figure 3. Delay and Reset Timing Table 5.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 5. MON_ and EN_OUT_ Assignment Registers (continued) REGISTER ADDRESS FLASH ADDRESS 84h 284h 85h 86h 285h 286h 87h 287h 88h 288h 89h 289h BIT RANGE DESCRIPTION [3:0] EN_OUT1 [7:4] EN_OUT2 [3:0] EN_OUT3 [7:4] EN_OUT4 [3:0] EN_OUT5 [7:4] EN_OUT6 [3:0] EN_OUT7 [7:4] EN_OUT8 [3:0] EN_OUT9 [7:4] EN_OUT10 [3:0] EN_OUT11 [7:4] EN_OUT12 Table 6.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 7.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers are MON1/MON2, MON3/MON4, MON5/MON6, MON7/ MON8, MON9/MON10, MON11/MON12 with the first input always being at a higher voltage than the second. Use differential voltage sensing to eliminate voltage offsets or measure supply current. See Figure 4.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 8.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 9. ADC Configuration Registers (continued) REGISTER ADDRESS 44h 45h 20 FLASH ADDRESS BIT RANGE DESCRIPTION [1:0] ADC5 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted [3:2] ADC6 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted [5:4] ADC7 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 9.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers When GPIO1–GPIO8 are configured as general-purpose inputs/outputs, read values from the GPIO_ ports through r1Eh and write values to GPIO_s through r3Eh. Note that r3Eh has a corresponding flash register, which programs the default state of a general-purpose output. See Table 11 for more information on reading and writing to the GPIO_.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 12.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers ANY_FAULT GPIO1, GPIO3, GPIO4, GPIO5, and GPIO7 are configurable to assert low during any fault condition. This includes power-up, power-down fault conditions as well as conditions where Fault1 or Fault2 assert. Second Enable (EN2) GPIO5 and GPIO7 are configurable as the enable input for the secondary sequence. See the Multiple Sequencing Groups section for more details. Table 14.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 14.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers External Fault (EXTFAULT) GPIO4 and GPIO8 are configurable as the external fault input/output. When configured as push-pull, EXTFAULT signals that a critical fault has occurred on one or more monitored voltages or current. When configured as open-drain, EXTFAULT can be asserted low by an external circuit to trigger a critical fault. This signal can be used to cascade multiple MAX16065/MAX16066s.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 15.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 16.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 17. Fault Flags (continued) REGISTER ADDRESS BIT RANGE 1Ch [0] MON9 [1] MON10 [2] MON11 [3] MON12 [4] Overcurrent [5] External fault (EXTFAULT) SMB alert [6] 1Dh DESCRIPTION [4:0] Slot where failure occurred during secondary sequence [7:5] Reserved Table 18.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 18.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 19.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Set r74h[4:3] to a value other than ‘00’ to select autoretry mode (see Table 20). In this configuration, the device shuts down after a critical fault event then restarts following a configurable delay. Use r74h[2:0] to select an autoretry delay from 20ms to 2s. See Table 20 for more information on setting the autoretry delay.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 21.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 21.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 22.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 23. Reset Output Configuration REGISTER ADDRESS FLASH ADDRESS BIT RANGE [1:0] 3Bh 0 = Active-low 1 = Active-high [3] 1 = Push-pull 0 = Open drain 23Bh 3Dh 23Ch 23Dh Reset Timeout Period: 0000 = 25Fs 0001 = 1.5ms 0010 = 2.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The normal watchdog timeout period, tWDI, begins after the first transition on WDI before the conclusion of the long startup watchdog period, tWDI_STARTUP (Figure 8). During the normal operating mode, WDO asserts if the FP does not toggle WDI with a valid transition (high-tolow or low-to-high) within the standard timeout period, tWDI.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers VCC < tWDI WDI tWDI tRP < tWDI_STARTUP < tWDI 0V VCC RESET 0V VCC WDO 0V 1µs Figure 10. Watchdog Startup Sequence with Watchdog Reset Output Enable Bit Set to ‘1’ Table 24.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 25. Memory Lock Bits REGISTER ADDRESS 8Ch FLASH ADDRESS BIT RANGE 0 Configuration Register Lock: 1 = Locked 0 = Unlocked 1 Flash Fault Register Lock: 1 = Locked 0 = Unlocked 2 Flash Configuration Lock: 1 = Locked 0 = Unlocked 3 User Flash Lock: 1 = Locked 0 = Unlocked 28Ch Independent Watchdog Timer Operation When r73h[4] is ‘1’ the watchdog timer operates in independent mode.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SDA SDA SCL SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID S P START CONDITION STOP CONDITION Figure 11. Bit Transfer Figure 12. START and STOP Conditions over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 26. SMBus Settings Register REGISTER ADDRESS FLASH ADDRESS 8Bh 28Bh BIT RANGE DESCRIPTION [6:0] SMBus Slave Address Register. Set to 00h to use A0 pin address setting. [7] 1 = Enable PEC (packet error check). Table 27. Setting the SMBus Slave Address SLAVE ADDRESSES A0 SLAVE ADDRESS 0 1010 000R 1 1010 001R SCL 1010 010R SDA 1010 011R R = Read/Write select bit. Table 28.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers 5) The addressed slave asserts an ACK (or NACK) on SDA. Restrictions When Writing to Flash Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries—the 3 LSBs of the initial address must be ‘000’. Write the 8 bytes using a single block-write command or using 8 successive Write Byte commands. 6) The master sends a STOP condition.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers page is currently selected. The write byte procedure is the following: 5) The addressed slave asserts an ACK on SDA. 6) The master sends a REPEATED START condition. 1) The master sends a START condition. 7) 2) The master sends the 7-bit slave address and a write bit (low). The master sends the 7-bit slave address and a read bit (high). 8) The addressed slave asserts an ACK on SDA.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers The block write procedure is the following: the configuration register or configuration flash or FFh in user flash, the address pointer stays at 8Fh or FFh, respectively. The block read procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers SMBALERT The MAX16065/MAX16066 support the SMBus alert protocol. To enable the SMBus alert output, set r35h[1:0] according to Table 29, which configures a Fault1, Fault2, or ANY_FAULT output to act as the SMBus alert. This output is open-drain and uses the wired-OR configuration with other devices on the SMBus.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Send Byte Format S ADDRESS Receive Byte Format R/W ACK 7 bits 0 COMMAND ACK 8 bits 0 0 Slave Address: Address of the slave on the serial interface bus. P ADDRESS S Data Byte: Presets the internal address pointer or represents a command. ADDRESS 7 bits SLAVE ADDRESS 0 DATA NACK 8 bits 1 P Data Byte: Data is read from the location pointed to by the internal address pointer.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers REGISTERS AND FLASH 01100 01011 01010 01001 01000 00111 MEMORY WRITE REGISTER [LENGTH = 8 BITS] 00110 MEMORY READ REGISTER [LENGTH = 8 BITS] 00101 MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] 00100 USER CODE REGISTER [LENGTH = 32 BITS] 00011 MUX 1 IDENTIFICATION REGISTER [LENGTH = 32 BITS] 00000 BYPASS REGISTER [LENGTH = 1 BIT] 11111 COMMAND DECODER 01001 SETFLSHADD 01010 RSTFLSHADD 01
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. Shift-IR: In this state, the shift register in the instruction register connects between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 1 SELECT-IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 0 1 0 1 UPDATE-IR 1 0 0 Figure 16. Tap Controller State Diagram Table 30.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 32. 32-Bit User-Code Data MSB LSB Don’t Care 00000000000000000 SMBus slave ID See Table 27 SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. The current ADC conversion results along with fault information are saved to flash depending on the configuration of the Critical Fault Log Control register (r6Dh).
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Table 33. Maximum Write Time r6Dh[1:0] VALUE MAXIMUM WRITE TIME (ms) DESCRIPTION 00 Save flags and ADC readings 244 01 Save flags 77 10 Save ADC readings 153 11 Do not save anything VIN VOUT R MON_ EN_OUT_ — MAX16065 MAX16066 VIN VCC C MAX16065 MAX16066 Figure 18. Connection for a p-Channel Series-Pass MOSFET GND Figure 17.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Figure 19. Graphical User Interface Screenshot slot on different devices will not come up in the desired order even if the sequence delays are identical. U Consider using an external FP to control the EN inputs or the software enable bits of cascaded devices, monitoring the RESET outputs as a power-good signal.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers This way a single pair of inputs can monitor the voltage and the current of a power-supply rail. The overvoltage threshold on the even-numbered MON_ inputs can be used as an overcurrent flag. Figure 20 shows how to connect a current-sense resistor to a pair of MON_ inputs for monitoring both current and voltage. For best accuracy, set the voltage range on the evennumbered MON_ to 1.4V.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map FLASH ADDRESS REGISTER ADDRESS READ/ WRITE DESCRIPTION ADC VALUES, FAULT REGISTERS, GPIO_s AS INPUT PORTS—NOT IN FLASH 54 — 000 R MON1 ADC output, MSBs — 001 R MON1 ADC output, LSBs — 002 R MON2 ADC output, MSBs — 003 R MON2 ADC output, LSBs — 004 R MON3 ADC output, MSBs — 005 R MON3 ADC output, LSBs — 006 R MON4 ADC output, MSBs — 007 R MON4 ADC out
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) FLASH ADDRESS REGISTER ADDRESS READ/ WRITE DESCRIPTION GPIO AND OUTPUT DEPENDENCIES/CONFIGURATIONS 230 030 R/W OUT configuration 231 031 R/W OUT configuration 232 032 R/W OUT configuration 233 033 R/W Charge-pump configuration, bits 234 034 R/W EN_OUT_ as GPIO data out 235 035 R/W SMBALERT pin configuration 236 036 R/W Fault1 dependencies 237 0
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) FLASH ADDRESS REGISTER ADDRESS READ/ WRITE 254 054 R/W MON5 secondary selectable UV/OV 255 055 R/W MON5 primary OV 256 056 R/W MON5 primary UV 257 057 R/W MON6 secondary selectable UV/OV 258 058 R/W MON6 primary OV 259 059 R/W MON6 primary UV 25A 05A R/W MON7 secondary selectable UV/OV DESCRIPTION 25B 05B R/W MON7 primary OV 25C 05C R/W M
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) FLASH ADDRESS REGISTER ADDRESS READ/ WRITE 278 078 R/W Sequence delay for Slot 2 and Slot 3 279 079 R/W Sequence delay for Slot 4 and Slot 5 27A 07A R/W Sequence delay for Slot 6 and Slot 7 DESCRIPTION 27B 07B R/W Sequence delay for Slot 8 and Slot 9 27C 07C R/W Sequence delay for Slot 10 and Slot 11 27D 07D R/W Primary sequence final slot, sequence
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Register Map (continued) USER FLASH 300 39F R/W User flash 3A0 3AF — Reserved 3B0 3FF R/W User flash Typical Operating Circuits VSUPPLY +3.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Typical Operating Circuits (continued) VSUPPLY +3.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers GPIO6 EN_OUT12 EN_OUT11 EN_OUT10 EN_OUT9 EN_OUT8 EN_OUT7 EN_OUT6 EN_OUT5 EN_OUT3 TOP VIEW EN_OUT4 EN_OUT2 Pin Configurations 36 35 34 33 32 31 30 29 28 27 26 25 GPIO5 EN_OUT1 37 24 EN 38 23 GPIO4 DBP 39 22 GPIO3 VCC 40 21 GPIO2 ABP 41 20 GPIO1 GND 42 19 GPIO8 MON7 43 18 GPIO7 MON8 44 17 GND MON9 45 16 SCL MON10 46 15 AO MON11 47 14 SDA MON12
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Chip Information PROCESS: BiCMOS Maxim Integrated Package Information For the latest package outline information and land patterns, (footprints) go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX16065/MAX16066 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers Revision History REVISION NUMBER REVISION DATE 0 7/09 Initial release 1 2/11 Made correction to Tables 6 and 23 2 8/11 Revised Electrical Characteristics, Detailed Description, and Figure 3 3 11/14 Corrected DBP, ABP to GND row in Absolute Maximum Ratings DESCRIPTION PAGES CHANGED — 16, 36 2, 4, 11, 15 2 Maxim Integrated cannot assume responsibility for use of any circuitry other than