9-4577; Rev 1; 8/09 KIT ATION EVALU E L B AVAILA 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers High-Current Voltage-Positioned Step-Down Converters MAX17030GTL+ MAX17036GTL+ BST2 LX2 DH2 DL1 DH1 30 29 28 27 26 25 24 23 22 21 Notebooks/Desktops/Servers PART LX1 TOP VIEW BST1 3 to 4 Li+ Cells Battery to CPU Core Supply Converters Pin Configuration DL2 IMVP-6.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ABSOLUTE MAXIMUM RATINGS (Note 1) VCC, VDD to GND .....................................................-0.3V to +6V D0–D6, PGD_IN, PSI, DPRSLPVR to GND ...............-0.3V to +6V CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V PWRGD, CLKEN, VR_HOT to GND..........................-0.3V to +6V FB, FBAC, IMON, TIME to GND .................-0.3V to (VCC + 0.3V) SHDN to GND (Note 2)...........................................
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER On-Time Accuracy SYMBOL t ON CONDITIONS VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) MIN TYP MAX RTON = 96.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 6.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Phases 2, 3 Disable Threshold CSP_, CSN_ Input Current ILIM Input Current CONDITIONS Measured at CSP2, CSP3 MIN TYP MAX UNITS 3 VCC 1 VCC 0.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = -40oC to +105°C, unless otherwise noted.) (Note 5) PARAMETER On-Time Accuracy SYMBOL t ON Minimum Off-Time t OFF(MIN) CONDITIONS VIN = 10V, VFB = 1.0V, measured at DH1, DH2, and PWM3 (Note 4) MIN TYP MAX RTON = 96.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, VIN = 10V, VCC = VDD = V SHDN = VPGD_IN = V PSI = VILIM = 5V, VDPRSLPVR = VGNDS = 0, VCSP_ = VCSN_ = 1.0000V, FB = FBAC, RFBAC = 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA = -40oC to +105°C, unless otherwise noted.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Note 3: The equation for the target voltage VTARGET is: VTARGET = The slew-rate-controlled version of VDAC, where VDAC = 0 for shutdown VDAC = VBOOT during IMVP-6.5 startup VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 4). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Typical Operating Characteristics (continued) (Circuit of Figure 1. VIN = 12V, VCC = VDD = 5V, SHDN = VCC, D0–D6 set for 0.95V, TA = +25°C, unless otherwise specified.) IIMON vs. LOAD CURRENT CURRENT BALANCE vs. LOAD CURRENT VOUT = 0.95V 0.1 VCSP3 VCSN3 0 VCSP2 - VCSN2 5 -0.1 VCS3 - VCS1 0 10 20 30 40 40 0 -0.2 50 60 0 70 40 30 50 0.8125V OUTPUT VOLTAGE DISTRIBUTION Gm(FB) TRANSCONDUCTANCE DISTRIBUTION 40 30 408 406 404 402 400 398 396 0.8175 0.8165 0.8155 0.8145 0 0.
1/2/3-Phase-Quick-PWM IMVP-6.5 VID Controllers SOFT-START WAVEFORM (UP TO CLKEN) SOFT-START WAVEFORM (UP TO PWRGD) MAX17030 toc12 3.3V 0 3.3V 0 0.95V MAX17030 toc13 A B C 3.3V 0 3.3V 0 3.3V 0 0.95V A B C D 0 0 0 D 0 E 0 E F 0 F 0 G 0 200μs/div 1ms/div D. ILX1, 10A/div E. ILX2, 10A/div F. ILX3, 10A/div IOUT, 15A A. SHDN, 5V/div B. CLKEN, 10V/div C. VOUT, 500mV/div SHUTDOWN WAVEFORM LOAD-TRANSIENT RESPONSE (HFM MODE) MAX17030 toc14 3.3V 0 3.3V 0 3.3V 0 0.95V E. DL1, 10V/div F.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 Pin Description PIN NAME FUNCTION CSN3 Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. 2 CSP3 Positive Input of the Output Current Sense of Phase 3.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers PIN NAME FUNCTION Output of the Voltage-Positioning Transconductance Amplifier.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 Pin Description (continued) PIN 15 NAME PSI FUNCTION This low-voltage logic input indicates power usage and sets the operating mode together with DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if PSI is forced low, the controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase forced-PWM mode when PSI is forced high.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers PIN NAME FUNCTION 20 PWM3 PWM Signal Output for Phase 3. Swings from GND to VDD. Three-state whenever phase 3 is disabled (in shutdown, when CSP3 is connected to VCC, and when operating with fewer than all phases). 21 BST2 Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 highside gate driver.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 Pin Description (continued) PIN NAME FUNCTION 40 CSN1 Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. A 10 discharge FET is turned on in UVLO event or thermal shutdown, or at the end of soft-shutdown.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers IMVP-6.5 XE CORE 3-PHASE DESIGN PARAMETERS IMVP-6.5 SV CORE 3-PHASE IMVP-6.5 SV CORE 2-PHASE Circuit Figure 1 Figure 1 Input Voltage Range 8V to 20V 8V to 20V 8V to 20V Maximum Load Current 65A (48A TDC) 52A (38A TDC) 52A (38A TDC) Transient Load Current 49A (100A/μs) 39A (100A/μs) 39A (100A/μs) Load Line -1.9mV/A -1.9mV/A -1.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Table 2. Component Suppliers MANUFACTURER WEBSITE MANUFACTURER WEBSITE AVX Corp. www.avxcorp.com Siliconix (Vishay) www.vishay.com Fairchild Semiconductor www.fairchildsemi.com Taiyo Yuden www.t-yuden.com NEC/TOKIN America, Inc. www.nec-tokinamerica.com TDK Corp. www.component.tdk.com Panasonic Corp. www.panasonic.com TOKO America, Inc. www.tokoam.com SANYO Electric Co., Ltd. www.sanyodevice.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers MAX17030/MAX17036 THRM VRHOT PWM3 PHASE 3 DRIVER CONTROL DRSKP CSN3 0.3 x VCC TRIG Q TRIG3 Gm(CCI) CSP3 TON CC13 ONE-SHOT PHASE 3 ON-TIME 10x CSN3 CSP3 CSP1 Gm(CCI3) CSN1 BST2 DH2 LX2 DL2 GND CSP2 10x PHASE 2 DRIVERS CSN2 CSP1 Q 10x CSN1 ILIM MINIMUM OFF-TIME TIME Q TRIG ONE-SHOT PHASE 2 ON-TIME CCI2 CSN2 TRIG TRIG 3 Gm(CCI) ONE SHOT VCC PHASE 1 ON-TIME ONE-SHOT REF (2.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Detailed Description Free-Running, Constant-On-Time PWM Controller with Input Feed-Forward The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor’s ESR to act as the currentsense resistor, so the output ripple voltage provides the PWM ramp signal.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ⎛V + 0.075V ⎞ t ON(SEC) = TSW ⎜ CCI ⎟⎠ VIN ⎝ ⎛ V + 0.07 ⎛ ICCIZ CCI ⎞ 75V ⎞ = TSW ⎜ FB ⎟⎠ + TSW ⎜⎝ V ⎟ VIN ⎝ IN ⎠ = (Main On-ttime) + ( Secondary Current Balance Correction) where V CCI is the internal integrator node for each slave’s current-balance integrator, and Z CCI is the effective impedance at that node. During phase overlap, t ON is calculated based on phase 1’s on-time requirements, but reduced by 33% when operating with three phases.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Feedback Adjustment Amplifiers Voltage-Positioning Amplifier (Steady-State Droop) The MAX17030/MAX17036 include a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated by summing the current-sense inputs, which differentially sense the voltage across either current-sense resistors or the inductor’s DCR.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers off-time expires. The on-time for each phase is based on the input voltage to FB ratio (i.e., follows the master on-time), but reduced by 33% in a 3-phase configuration, and not reduced in a 2-phase configuration. This maximizes the total inductor current slew rate. After the phase-overlap mode ends, the controller automatically begins with the next phase.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers INPUTS SHDN PSI DPRSLPVR Falling X High X X PHASE OPERATION* OPERATING MODE Multiphase Forced-PWM 1/4 RTIME Slew Rate Shutdown. When SHDN is pulled low, the MAX17030/MAX17036 immediately pull PWRGD low, CLKEN becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to 12.5mV; then DH and DL are pulled low and CSN1 discharge FET is turned on. X Fault Mode.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Table 4. IMVP-6.5 Output Voltage VID DAC Codes (continued) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE (V) 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Output-Voltage-Transition Timing At the beginning of an output-voltage transition, the MAX17030/MAX17036 blank both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the lower PWRGD threshold approximately 20μs after the slew-rate controller reaches the target output voltage, but the upper PWRGD threshold is enabled only if the controller remains in forced-PWM operation.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers ACTUAL VOUT CPU CORE VOLTAGE INTERNAL TARGET VID (D0–D6) DEEPER SLEEP VID DPRSLPVR PSI INTERNAL PWM CONTROL DO NOT CARE (DPRSLPVR DOMINATES STATE) 1-PHASE SKIP (DH1 ACTIVE, DH2, DL2 FORCED LOW, PWM3 THREE-STATE) DH1 FORCED-PWM NO PULSES: VOUT > VTARGET DH2 PWM3 PWRGD BLANK HIGH-Z BLANK HIGH THRESHOLD ONLY BLANK HI-Z CLKEN BLANK LOW BLANK HIGH THRESHOLD ONLY BLANK LO SET TO 1.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Forced-PWM Operation (Normal Mode) During soft-shutdown and normal operation—when the CPU is actively running (DPRSLPVR = low, Table 5)— the MAX17030/MAX17036 operate with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gatedrive waveforms.
When pulse-skipping, the controller blanks the upper PWRGD and CLKEN thresholds. Upon entering pulseskipping operation, the controller temporarily sets the OVP threshold to 1.5V, preventing false OVP faults when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers t TRAN(START) = 4VBOOT (dVTARGET dt ) where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. CLKEN is pulled low approximately 60μs after the MAX17030/MAX17036 reach the boot voltage. At the same time, the MAX17030/MAX17036 slew the output to the voltage set at the VID inputs at the programmed slew rate.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers during a downward VID transition in skip mode. During pulse-skipping operation (DPRSLPVR = high), the OVP threshold tracks the VID DAC voltage as soon as the output is in regulation; otherwise, the fixed 1.5V (typ) threshold is used.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers BST_ INPUT (VIN) CBST DH_ NH L LX_ CBYP VDD DL_ For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase: NL (CNL)* PGND I ILOAD(PHASE) = LOAD η TOTAL MAX17030/MAX17036 (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must not to saturate at the peak inductor current (IPEAK): ⎛ ILOAD(MAX) ⎞ ⎛ LIR ⎞ IPEAK = ⎜ ⎟ ⎜ 1 + 2 ⎟⎠ ⎝ η TOTAL ⎠ ⎝ Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers Transient Response The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers The optimum high-side MOSFET trades the switching losses with the conduction (RDS(ON)) losses over the input voltage range. Ideally, the losses at V IN(MIN) should be roughly equal to losses at VIN(MAX) , with lower losses in between. If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses.
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers I VALLEY = VLIMIT R SENSE where RSENSE is the sensing resistor or effective inductor DCR. Voltage Positioning and Loop Compensation Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power-dissipation requirements. The MAX17030/MAX17036 use a transconductance amplifier to set the transient and DC output voltage droop (Figure 3) as a function of the load.
MAX17030/MAX17036 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers 4) Make the DC-DC controller ground connections as shown in the standard application circuits.
1/2/3 Phase-Quick-PWM IMVP-6.5 VID Controllers REVISION NUMBER REVISION DATE 0 4/09 Initial release 1 8/09 Updated the Pin Description, Figure 3, Table 3, and the Power-Up Sequence (POR, UVLO), Shutdown Output Undervoltage Protection, and Thermal-Fault Protection sections. DESCRIPTION PAGES CHANGED — 13, 14, 19, 25, 31, 32 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.