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General Description

The MAX17103 includes a high-performance step-up

regulator, a 350mA low-dropout linear regulator, a high-

speed operational amplifier, a negative linear regulator

controller, and a high-voltage, level-shifting scan driver.

The device is optimized for thin-film transistor (TFT) liq-

uid-crystal display (LCD) applications.

The step-up DC-DC converter provides the regulated

supply voltage for panel source driver ICs. The high

1.2MHz switching frequency allows the use of ultra-

small inductors and ceramic capacitors. The current-

mode control architecture provides fast-transient

response to pulsed loads typical of source driver loads.

The step-up regulator features an adjustable soft-start

and an adjustable cycle-by-cycle current limit.

The high-current operational amplifier is designed to

drive the LCD backplane (VCOM). The amplifier fea-

tures high output current (±200mA), fast slew rate

(50V/µs), wide bandwidth (12MHz), and rail-to-rail

inputs and outputs.

The low-voltage LDO linear regulator has an integrated

0.8Ω pass element and can provide at least 350mA.

The output voltage is accurate within ±1%.

The high-voltage, level-shifting scan driver is designed to

drive the TFT panel gate drivers. Its three outputs can

swing up to 40V (max) to swiftly drive capacitive loads. To

save power, the two complementary outputs are designed

to allow charge sharing during state changes.

The MAX17103 is available in a 32-pin, 5mm x 5mm,

thin QFN package with a maximum thickness of 0.8mm

for thin LCD panels.

Applications

Notebook Computer Displays

Features

o 2.3V to 5.5V IN Supply Voltage Range

o 1.2MHz Current-Mode Step-Up Regulator

Fast-Transient Response

High-Accuracy Reference (1%)

Integrated 16V, 2A, 200mΩ MOSFET

High Efficiency (> 85%)

Adjustable Cycle-by-Cycle Current Limit

o High-Performance Operational Amplifier

200mA Output Short-Circuit Current

50V/µs Slew Rate

12MHz, -3dB Bandwidth

o Low-Dropout Linear Regulator

High-Accuracy Output Voltage (1.0%)

o High-Voltage Drivers with Scan Logic

+35V to -15V Outputs

40V (Max) Swing

o Linear Regulator Controller for Gate-Off Supply

o Thermal-Overload Protection

o 32-Pin, 5mm x 5mm, Thin QFN Package

MAX17103/AUO-P1721.14

DC-DC Converter with Integrated Scan Driver,

VGL Controller, Op Amp, and LDO for TFT LCD

________________________________________________________________

Maxim Integrated Products

Ordering Information

GHON

MAIN

To VCOM

BACKPLANE

VGL

LOGIC

GHON

COMP

PGND

LDOO

LDOADJ

ENA

OPAS

POS

OUT

VDET

AGND

GHON

VGL

VGLC

FBN

REF

DRVN

XCK

STH

CKH

XCKH

SYSTEM

RST

PANEL

VGL

CONTROLLER

STEP-UP

CONTROLLER

LINEAR

REGULATOR

VOLTAGE

DETECTOR

SCAN

DRIVER

LOGIC

VGL

GHON

MAX17103

AUO-P1721.14

Simplified Operating Circuit

19-4445; Rev 0; 2/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX17103ETJ+ -40°C to +85°C 32 Thin QFN-EP*

AUO-P1721.14 -40°C to +85° C 32 Thin QFN-EP*

Denotes lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

Pin Configuration appears at end of data sheet.

Summary of content (27 pages)

PAGE 1
9-4445; Rev 0; 2/09 KIT ATION EVALU LE B A IL A AV DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD The MAX17103 includes a high-performance step-up regulator, a 350mA low-dropout linear regulator, a highspeed operational amplifier, a negative linear regulator controller, and a high-voltage, level-shifting scan driver. The device is optimized for thin-film transistor (TFT) liquid-crystal display (LCD) applications.
PAGE 2
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD ABSOLUTE MAXIMUM RATINGS IN, RST to AGND ...................................................-0.3V to +7.5V FB, FBN, CD, ENA, VDET, SS, CS, ST, CK, XCK to AGND...................................-0.3V to (VIN + 0.3V) LDOADJ, LDOO, COMP, REF to AGND ......-0.3V to (VIN + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V LX, OPAS to PGND............................
PAGE 3
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER CONDITIONS LX On-Resistance ILX = 1A LX Leakage Current VLX = 13.5V, TA = +25°C Current-Sense Transresistance Soft-Start Pullup Current GATE-OFF LINEAR REGULATOR CONTROLLER FBN Fault Trip Level VFBN rising FBN Regulation Voltage IDRVN = 100μA FBN Line-Regulation Error VIN = 2.5V to 5.
PAGE 4
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD ELECTRICAL CHARACTERISTICS (continued) (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER IN Input-Voltage Range CONDITIONS (Note 1) IN Undervoltage-Lockout Threshold VIN rising, typical hysteresis = 150mV IN Standby Current IN Quiescent Current GHON Standby Current OPAS Shutdown Current MIN MAX UNITS 2.3 5.5 V 1.80 2.20 V 2 mA VENA = 0, VIN = 5.5V, VGHON = 4V, VGL = 0 VFB = 1.
PAGE 6
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD ELECTRICAL CHARACTERISTICS (continued) (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS VCOM BUFFER Supply Voltage VOPAS OPAS Supply Current VPOS = V OPAS/2, no load 6 I OUT = 100μA VOPAS - 0.02 I OUT = 75mA VOPAS - 1.5 15 V 5 mA VOPAS - 0.
PAGE 7
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD (VIN = +3V, Circuit of Figure 1, VOPAS = +8.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 400 1 mA 500 mV CHARGE-SHARING FUNCTION QS-to-CKH On-Resistance VGHON = 24V, VVGL = -6V; VCKH = VXCKH = 10V, CS = low GHON - QS Switch Leakage Current CS = low LOW-DROPOUT LINEAR REGULATOR Dropout Voltage VIN = 3.3V, VLDOADJ = 1.1V, I OUT = 0.
PAGE 8
Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 80 70 VIN = 2.3V 60 0 VIN = 5.0V -0.1 -0.2 VIN = 3.0V -0.3 4.0 VMAIN = 8.5V 40 10 1 100 2.5 NOT SWITCHING 2.0 1.5 1.0 0.5 0 1 10 1.6 1000 100 2.7 4.9 6.0 STEP-UP CONVERTER SWITCHING FREQUENCY vs. INPUT VOLTAGE STEP-UP CONVERTER PEAK INDUCTOR CURRENT LIMIT vs. RENA 2.5 2.0 VIN = 3.3V 1.5 1.0 VMAIN = 8.5V IMAIN = NO LOAD VLDOO = 2.5V ILDOO = NO LOAD 0.5 0 -15 10 35 60 MAX17103 toc05 1.
PAGE 9
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD LDO OUTPUT LOAD REGULATION vs. LOAD CURRENT STEP-UP REGULATOR PULSED LOADTRANSIENT RESPONSE (20mA TO 1A) MAX17103 toc09 VLX 10V/div 0A IL1 500mA/div VMAIN (AC-COUPLED) 500mV/div 0mV MAX17103 toc10 0V OUTPUT ERROR (%) 0.2 0 VIN = 3.0V -0.2 VIN = 5.0V IMAIN 1A/div -0.4 1 10μs/div L1 = 10μH LDO LINE REGULATION vs. INPUT VOLTAGE -0.04 VIN 5V/div VLDOO 5V/div VREF 5V/div 0V 0V -0.
PAGE 10
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.
PAGE 11
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD STH FALLING EDGE PROPAGATION DELAY CS/CKH RISING EDGE PROPAGATION DELAY MAX17103 toc23 MAX17103 toc24 VST 5V/div 0V VCS 5V/div 0V VSTH 10V/div VCKH 10V/div 0V 0V CLOAD = 100pF CLOAD = 3.4nF AND 50Ω 40ns/div 20ns/div CS/CKH FALLING EDGE PROPAGATION DELAY SCAN DRIVER OUTPUT RISE TIME MAX17103 toc25 MAX17103 toc26 VCS 5V/div VST 5V/div 0V 0V VSTH 10V/div 0V VCKH 10V/div 0V CLOAD = 3.
PAGE 12
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD MAX17103/AUO-P1721.14 Pin Description PIN 12 NAME FUNCTION Operational Amplifier Supply Input. Connect to VMAIN (Figure 1) and bypass to AGND with a 0.1μF or greater ceramic capacitor. 1 OPAS 2 POS Operational Amplifier Noninverting Input 3 CS Charge-Sharing Control Input. Charge sharing between the capacitive loads of CKH and XCKH occurs when CS is low. 4 XCK Level-Shifter Input Signal.
PAGE 13
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD PIN NAME 21 VDET FUNCTION 22 SS 23 COMP Compensation Pin for Error Amplifier. Connect a series RC from this pin to AGND. Typical values are 56k and 1000pF. 24 FB Step-Up Regulator Feedback Pin. Reference voltage is 1.24V nominal. Connect an external resistor-divider midpoint to FB and minimize trace area. Set VMAIN according to VMAIN = 1.24V (1 + R1/R2).
PAGE 14
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD D3 VGHON 23V, 10mA 0.1μF 0.22μF 0.1μF VVGL -6.0V, 10mA D2 Q1 D4 0.1μF 0.22μF 1μF 0.1μF 0.1μF 6.81kΩ L1 10μH D1 VMAIN 8.5V, 250mA VIN C3 10μF C2 1μF R9 243kΩ DRVN IN FBN LX REF PGND R10 49.9kΩ RENA 62kΩ 0.22μF FB ENA COMP SS LDOADJ R7 51.1kΩ R8 49.9kΩ C4 10μF C5 10μF C6 10μF R1 102kΩ RCOMP 56.2kΩ CSS 330nF CCOMP 1000pF R2 17.4kΩ AGND VLOGIC (2.
PAGE 15
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD MAX17103/AUO-P1721.14 VGHON VVGL VMAIN VIN DRVN IN LX FBN VGL CONTROLLER PGND REF STEP-UP CONTROLLER ENA FB COMP SS LDOADJ LINEAR REGULATOR MAX17103 AUO-P1721.14 LDOO VLOGIC OPAS VDET CD RST VGHON AGND OP VOLTAGE DETECTOR OUT TO VCOM BACKPLANE POS GHON CKH CK CS SYSTEM QS XCK ST XCKH SCAN DRIVER LOGIC PANEL STH VGLC VGHON GD VVGL VGL Figure 2.
PAGE 16
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Typical Application Circuit The MAX17103 typical application circuit (Figure 1) generates a +8.5V source-driver supply and approximately +23V and -6V gate-driver supplies for TFT displays. The input-voltage range for the IC is from +2.3V to +5.5V, but the circuit in Figure 1 is designed to run from 2.5V to 3.6V. Table 1 lists the recommended components and Table 2 lists the component suppliers.
PAGE 17
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD MAX17103/AUO-P1721.14 LX CLOCK LOGIC AND DRIVER PGND ILIM COMPARATOR SOFTSTART ILIMIT SLOPE COMPENSATION PWM COMPARATOR OSCILLATOR CURRENT SENSE ERROR AMP FB 1.24V COMP Figure 3. Step-Up Regulator Block Diagram Undervoltage Lockout (UVLO) The UVLO circuit compares the input voltage at IN with the UVLO threshold (2.0V typ) to ensure that the input voltage is high enough for reliable operation.
PAGE 18
Operational Amplifier a pure capacitive load, steps must be taken to ensure stable operation. As the operational amplifier’s capacitive load increases, the amplifier’s bandwidth decreases and gain peaking increases. A 5Ω to 50Ω small resistor placed between VCOM and the capacitive load reduces peaking, but also reduces the gain. An alternative method of reducing peaking is to place a series RC network (snubber) in parallel with the capacitive load.
PAGE 19
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD below 2.0V (typ), the CKH and XCK outputs are driven to VGHON regardless of the state of the CK and XCK inputs to discharge the panel. The STH driver output is determined by the ST input except during power-down. During power-down, if VMAIN has exceeded 90% of its regulation voltage for more than 64ms prior to the power-down, the STH output goes high impedance during the power-down once either VVDET falls below 1.
PAGE 20
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD The CK and XCK inputs are normally configured to drive the CKH and XCKH outputs complementary as shown in Figure 5. The CS input is normally configured to be driven low for a period of time that overlaps the CK and XCK input transitions.
PAGE 21
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Voltage Detector The voltage detector monitors either VIN or VLDOO to generate a logic-low system reset signal (RST) and to discharge the panel once the voltage being monitored falls below a desired threshold. The voltage being monitored is sensed through a resistor-divider whose midpoint is connected to VDET. Once VVDET falls below 1.
PAGE 22
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD VOLTAGE POWER-UP POWER-DOWN VIN VIN 0 VLDOO 0 LDOO VLDOO x R6/(R5 + R6) 1.1V + 50mV 1.1V 0 VDET VLDOO tDELAY = 120k x CCD RST 0 TIME Figure 7. Voltage-Detector Power-Up and Power-Down Timing Low-Dropout Linear Regulator (LDO) The MAX17103 has an integrated 0.8Ω pass element and can provide at least 350mA. The output voltage is accurate within ±1%.
PAGE 23
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Design Procedure Main Step-Up Regulator Inductor Selection The minimum inductance value, peak current rating, and series resistance are factors to consider when selecting the inductor. These factors influence the converter’s efficiency, maximum output load capability, transientresponse time, and output-voltage ripple. Physical size and cost are also important factors to be considered.
PAGE 24
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD The inductor’s saturation current rating and the MAX17103 LX current limit should exceed IPEAK and the inductor’s DC current rating should exceed IIN(DC,MAX). For good efficiency, choose an inductor with less than 0.1Ω series resistance. Considering the typical operating circuit, the maximum load current (IMAIN(MAX)) is 250mA, with an 8.5V output and a typical input voltage of 3.3V.
PAGE 25
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Adjust the delay between the time V DETECT has reached its rising threshold set by R5 and R6 above and the time RST goes high by connecting a capacitor between CD and AGND with the following equation: For low-ESR output capacitors, use the following equations to obtain stable performance and good transient response: T CCD = DELAY 120kΩ R COMP ≈ C COMP ≈ 400 × VIN × VMAIN × C OUT L × IMAIN(MAX) 40 × VMAIN× L × IMAIN
PAGE 26
MAX17103/AUO-P1721.14 DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Operational Amplifier The power dissipated in the operational amplifier depends on the output current, the output voltage, and the supply voltage: ( PDSOURCE = IVCOM _ SOURCE × VAVDD - VVCOM ) PDSINK = IVCOM _ SINK × VVCOM where IVCOM_SOURCE is the output current sourced by the operational amplifier, and IVCOM_SINK is the output current that the operational amplifier sinks.
PAGE 27
DC-DC Converter with Integrated Scan Driver, VGL Controller, Op Amp, and LDO for TFT LCD Chip Information PROCESS: BiCMOS FB COMP SS VDET CD DRVN FBN REF 24 23 22 21 20 19 18 17 TOP VIEW Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PGND 25 16 RST LX 26 15 GD PACKAGE TYPE PACKAGE CODE DOCUMENT NO. ENA 27 14 N.C.