9-4443; Rev 0; 2/09 KIT ATION EVALU E L B AVAILA AMD 2-/3-Output Mobile Serial VID Controller The MAX17480 is a triple-output, step-down, fixedfrequency controller for AMD’s serial VID interface (SVI) CPU and northbridge (NB) core supplies. The MAX17480 consists of two high-current SMPSs for the CPU cores and one 4A internal switch SMPS for the NB core. The two CPU core SMPSs run 180° out-of-phase for true interleaved operation, minimizing input capacitance.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller ABSOLUTE MAXIMUM RATINGS (Note 1) VDD, VIN3, VCC, VDDIO to AGND ..............................-0.3V to +6V LX2 to BST2..............................................................-6V to +0.3V PWRGD to AGND .....................................................-0.3V to +6V LX3 to PGND (Note 2) ..............................................-0.6V to +6V SHDN to AGND ........................................................-0.3V to +6V DH1 to LX1 ...........
AMD 2-/3-Output Mobile Serial VID Controller (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Shutdown Supply Currents (VDD) SHDN = GND, TA = +25°C 0.01 1 µA Shutdown Supply Current (VDDIO) SHDN = GND, TA = +25°C 0.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
AMD 2-/3-Output Mobile Serial VID Controller (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM mode 250 300 350 mV Skip mode and output has not reached the regulation voltage 1.80 1.85 1.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS IDH_ DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.2 A IDL_ DL_ forced to 2.5V 2.
AMD 2-/3-Output Mobile Serial VID Controller (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUT SUPPLIES VIN 26 4.5 5.5 2.7 5.5 VDDIO 1.0 2.7 VCC rising, 50mV typical hysteresis, latched, UV fault 4.10 4.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
AMD 2-/3-Output Mobile Serial VID Controller (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FAULT DETECTION PWM mode 250 350 mV Skip mode and output have not reached the regulation voltage 1.80 1.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND, FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.
AMD 2-/3-Output Mobile Serial VID Controller 7V PWM MODE 12V 80 20V 70 20V 80 12V 70 VIN = 12V OUTPUT VOLTAGE (V) 90 EFFICIENCY (%) 90 1.205 MAX17480 toc02 100 MAX17480 toc01 100 EFFICIENCY (%) CORE SMPS OUTPUT VOLTAGE vs. LOAD CURRENT (VOUT = 1.2V) CORE SMPS 2-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2V) MAX17480 toc03 CORE SMPS 1-PHASE EFFICIENCY vs. LOAD CURRENT (VOUT = 1.2V) 1.200 SKIP MODE AND PWM MODE 1.
Typical Operating Characteristics (continued) (Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.) ICC + IDD 1 IIN 0.1 SKIP MODE PWM MODE VOUT = 1.2V 9 INPUT VOLTAGE (V) 12 15 18 21 24 INPUT VOLTAGE (V) MAX17480 toc12 1.205 6 1.204 0 3 20.0 1.203 17.5 20 1.202 15.0 30 1.201 12.5 40 1.200 10.0 50 1.195 7.5 60 10 0.01 5.0 70 1.199 21 SAMPLE SIZE = 100 TA = +85°C TA = +25°C 1.198 23 80 1.197 DC CURRENT 25 10 90 1.
AMD 2-/3-Output Mobile Serial VID Controller STARTUP SEQUENCE STARTUP WAVEFORMS MAX17480 toc17 MAX17480 toc16 SHDN, 5V/div VOUT1, 0.5V/div VOUT2, 0.5V/div VOUT3, 0.5V/div 0 0 0 0 SHDN, 5V/div VOUT1, 0.5V/div VOUT2, 0.5V/div 0 VOUT3, 0.5V/div 0 PWRGD, 5V/div 0 5A ILX, 5A/div 0 1A ILX3, 1A/div 0 0 PWRGD, 5V/div 0 0 0 PGD_IN, 2.5V/div SVC, 2.5V/div 0 SVD, 2.5V/div 0 400µs/div 200µs/div VIN = 12V VBOOT = 1V VIN = 12V VBOOT = 1V VSVID = 1.2V ILOAD1 = 3A ILOAD2 = 3A ILOAD3 = 0.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Typical Operating Characteristics (continued) (Circuit of Figure 2, VIN = 12V, VDD = VCC = 5V, VDDIO = 2.5V, TA = +25°C, unless otherwise noted.) CORE SMPS 2-PHASE LOAD-TRANSIENT RESPONSE CORE SMPS 1-PHASE TRANSIENT PHASE REPEAT MAX17480 toc21 MAX17480 toc20 VOUT1 50mV/div 1.2V VOUT 50mV/div 1.2V 13.5A 13.5A ILX1 10A/div 1.5A ILX1 10A/div 1.5A 13.5V 12V LX1 10V/div 0 1.5A ILX2 10A/div 20µs/div 2µs/div VIN = 12V VOUT1 = 1.
AMD 2-/3-Output Mobile Serial VID Controller CORE SMPS OUTPUT OVERLOAD WAVEFORM (SEPARATE MODE) CORE SMPS OUTPUT OVERVOLTAGE WAVEFORM (SEPARATE MODE) MAX17480 toc24 MAX17480 toc25 5V 5V SHDN, 5V/div 1.2V SHDN, 5V/div 1.2V VOUT1, 1V/div 5V 0 1.2V VOUT1, 1V/div 5V 0 1.2V VOUT2, 1V/div DL2, 10V/div 5V 0 1.2V VOUT2, 1V/div DL2, 10V/div 5V 0 VOUT3, 1V/div LX3, 10V/div 5V 0 VOUT3, 1V/div LX3, 10V/div DL1, 10V/div DL1, 10V/div 0 1.2V 100µs/div VIN = 12V VSVID = 1.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Pin Description PIN 1 NAME ILIM12 FUNCTION SMPS1 and SMPS2 Current-Limit Adjust Input. The positive current-limit threshold voltage is 0.052 times the voltage between TIME and ILIM over a 0.2V to 1.0V range of V(TIME, ILIM). The IMIN12 minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage. SMPS3 Current-Limit Adjust Input. Two-level current-limit setting for SMPS3.
AMD 2-/3-Output Mobile Serial VID Controller PIN NAME FUNCTION Output of the Voltage-Positioning Transconductance Amplifier for SMPS2.
AMD 2-/3-Output Mobile Serial VID Controller MAX17480 Pin Description (continued) PIN NAME FUNCTION Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS outputs. PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage transitions). 20 PWRGD During startup, PWRGD is held low for an additional 20µs after the MAX17480 reaches the startup boot voltage set by the SVC and SVD pins.
AMD 2-/3-Output Mobile Serial VID Controller PIN NAME FUNCTION 33 CSP1 Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. 34 CSN1 Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
AMD 2-/3-Output Mobile Serial VID Controller MAX17480 Pin Description (continued) PIN NAME FUNCTION Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching frequency (per phase): f OSC = 300kHz x 143k /R OSC 39 OSC A 71.4k to 432k resistor corresponds to switching frequencies of 600kHz to 100kHz, respectively, for SMPS1 and SMPS2. SMPS3 runs at twice the programmed switching frequency. Switching frequency selection is limited by the minimum on-time.
AMD 2-/3-Output Mobile Serial VID Controller COMPONENT VIN = 7V TO 24V, V OUT1 = VOUT2 = 1.0V TO 1.3V, 18A PER PHASE VIN3 = 5V, V OUT3 = 1.0V TO 1.3V, 4A VIN = 4.5V TO 14V, V OUT1 = VOUT2 = 1.0V TO 1.3V, 18A PER PHASE VIN3 = 3.3V, V OUT3 = 1.0V TO 1.3V, 4A Mode Separate, 2-phase mobile (GNDS1 = GNDS2 = low) — Separate, 2-phase mobile (GNDS1 = GNDS2 = low) — Switching Frequency 300kHz 600kHz 500kHz 1MHz CIN_ Input Capacitor (2) 10µF, 25V Taiyo Yuden TMK432BJ106KM (1) 10µF, 6.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller RVCC 10Ω CVCC 2.2µF 25 32 ROSC 39 40 VDD VCC BST1 OSC DH1 1 13 1.5V OR 1.8V 12 SERIAL INPUT 11 19 SYSTEM POWER-GOOD 8 ON OFF OPTION OFFSET SMPS1 ADDR VCC 3.
AMD 2-/3-Output Mobile Serial VID Controller MAX17480 RVCC 10Ω CVCC 2.2µF 25 32 ROSC 39 40 VDD VCC BST1 OSC DH1 1 13 1.5V OR 1.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller VRHOT 0.3 x VCC SHDN FAULT1 FAULT2 FAULT3 MAX17480 THRM VDDIO VCC VDD x2 REF (2.
AMD 2-/3-Output Mobile Serial VID Controller The MAX17480 consists of a dual fixed-frequency PWM controller with external switches that generate the supply voltage for two independent CPU cores and one low-input-voltage internal switch SMPS for the separate NB SMPS. The CPU core SMPSs can be configured as independent outputs, or as a combined output by connecting the GNDS1 or GNDS2 pin-strap high (GNDS1 or GNDS2 pulled to 1.5V to 1.8V, which are the respective voltages for DDR3 and DDR2).
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Transient Phase Repeat When a transient occurs, the output voltage deviation depends on the controller’s ability to quickly detect the transient and slew the inductor current. A fixed-frequency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. To minimize this delay time, the MAX17480 includes enhanced transient detection and transient phase repeat capabilities.
AMD 2-/3-Output Mobile Serial VID Controller where VCS = VCSP - VCSN is the differential currentsense voltage, and G m(FBAC) is 2.06mS (max) as defined in the Electrical Characteristics table. AC droop is required for stable operation of the MAX17480. A minimum of 1.5mV/A is recommended. AC droop must not be disabled.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Nominal Output-Voltage Selection Core SMPS Output Voltage The nominal no-load output voltage (VTARGET) for each SMPS is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (VGNDS) and the offset voltage (VOFFSET) as defined in the following equation: VTARGET = VFBDC = VDAC + VGNDS + VOFFSET where VDAC is the selected VID voltage of the core SMPS DAC, VGNDS is the ground-sense correction voltage for core supplies,
AMD 2-/3-Output Mobile Serial VID Controller BUS IDLE SMPS LOAD BUS IDLE BUS IDLE LIGHT LOAD PWRGD UPPER THRESHOLD MAX17480 SVC/SVD HEAVY LOAD UPPER THRESHOLD BLANKED SMPS TARGET SMPS VOLTAGE (SMPS TARGET) PWRGD LOWER THRESHOLD PWRGD BLANK HIGH-Z 20µs BLANK HIGH-Z 20µs BLANK HIGH-Z 20µs Figure 6. VID Transition Timing of a downward VID transition, the upper PWRGD threshold is enabled only after the output reaches the lower VID code setting. Figure 6 shows VID transition timing.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor could switch the controller to a low-power pulse-skipping control scheme. Pulse-Skipping Operation During soft-start and in power-saving mode—when the PSI_L bit is set to 0—the MAX17480 operates in pulseskipping mode.
AMD 2-/3-Output Mobile Serial VID Controller SVID[6:0] OUTPUT VOLTAGE (V) SVID[6:0] OUTPUT VOLTAGE (V) SVID[6:0] OUTPUT VOLTAGE (V) SVID[6:0] OUTPUT VOLTAGE (V) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 000_0100 1.5000 010_0100 1.1000 100_0100 0.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller INPUT (VIN) CIN DH_ SENSE RESISTOR NH L LESL RSENSE LX_ CEQREQ = COUT DL_ NL DL LESL RSENSE CEQ REQ MAX17480 CSP_ CSN_ A) OUTPUT SERIES RESISTOR SENSING INPUT (VIN) CIN DH_ INDUCTOR NH L RCS = RDCR R2 × RDCR R1 + R2 LX_ COUT DL_ NL DL R1 RLX CLX MAX17480 CSP_ CSN_ R2 RDCR = L 1 1 × + CEQ R1 R2 CEQ FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.
AMD 2-/3-Output Mobile Serial VID Controller Peak Current Limit The MAX17480 current-limit circuit employs a fast peak inductor current-sensing algorithm. Once the currentsense signal of the SMPS exceeds the peak current-limit threshold, the PWM controller terminates the on-time. See the Core Peak Inductor Current Limit (ILIM12) section in the Core SMPS Design Procedure section.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V. If the VCC voltage drops below 4.
AMD 2-/3-Output Mobile Serial VID Controller MAX17480 PULSE-SKIPPING MODE PSI_L SVC/SVD BUS IDLE SMPS VOUT (HIGH DAC TARGET) TARGET BUS IDLE 2-BIT BOOT VID, SVC/SVD INPUTS DISABLED VOUT (LOW DAC TARGET) SMPS VOUT PGD_IN BLANK HIGH-Z PWRGD BLANK HIGH-Z 20µs 20µs Figure 9. PGD_IN Timing RPTC1 VCC RTHRM PLACE RNTC NEXT TO THE HOTTEST POWER COMPONENT. VCC RPTC2 MAX17480 THRM RNTC PLACE RPTC1, RPTC2, AND RPTC3 NEXT TO THE RESPECTIVE SMPS'S POWER COMPONENT.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Fault Protection (Latched) Output Overvoltage Protection (OVP) The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17480 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV.
AMD 2-/3-Output Mobile Serial VID Controller enabled, setting the PSI_L bit to 0 disables the offset, reducing power consumption in the low-power state. See the Core SMPS Offset section for a detailed description of this feature. In addition, the address of the core SMPSs can be exchanged, allowing for flexible layout of the MAX17480 with respect to the CPU placement on the same or opposite sides of the PCB. Table 5 shows the OPTION pin voltage levels and the features that are enabled.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Table 6. ILIM3 Setting ILIM3 PEAK CURRENT LIMIT (A) SKIP CURRENT LIMIT (A) MAX DC CURRENT (A) FULL-LOAD DROOP (mV) OFFSET (mV) VCC 5.25 1.3 4.75 -26.13 12.5 GND 4.25 1.05 3.75 -20.63 12.5 Offset and Current-Limit Setting for NB SMPS (ILIM3) The offset and current-limit settings of the NB SMPS can be set by the ILIM3 pin setting.
AMD 2-/3-Output Mobile Serial VID Controller Core Inductor Selection By design, the AMD mobile serial VID application should regard each of the MAX17480 SMPSs as independent, single-phase SMPSs. The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: ⎛ ⎞⎛ V ⎞ VIN − VOUT ⎟ ⎜ OUT ⎟ L = ⎜⎜ ⎟ ⎝ fSWI LOAD(MAX)LIR ⎠ ⎝ VIN ⎠ where ILOAD(MAX) is the maximum current per phase, and fSW is the switching frequency per phase.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. Core Input Capacitor Selection The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents.
AMD 2-/3-Output Mobile Serial VID Controller Core MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: ⎛V ⎞ PD (NH Resistive) = ⎜ OUT ⎟ ILOAD2RDS(ON) ⎝ V ⎠ IN where ILOAD is the per-phase current. Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates: CBST = N × QGATE 200mV where N is the number of high-side MOSFETs used for one SMPS, and QGATE is the gate charge specified in the MOSFET’s data sheet. For example, assume two IRF7811W n-channel MOSFETs are used on the high side.
AMD 2-/3-Output Mobile Serial VID Controller VSOAR3 2 ∆I LOAD3(MAX) ) L3 ( = 2VOUT3COUT3 ( ∆ILOAD3(MAX) ) 2 : VSAG3 = 2C ( L3 OUT 3 VIN3 × DMAX − VOUT 3 ) + ∆I LOAD3(MAX)( tSW 3 − ∆t ) COUT3 where D MAX is the maximum duty cycle of the NB SMPS as listed in the Electrical Characteristics table, tSW3 is the NB switching period programmed by the OSC pin, and ∆t equals VOUT/VIN x tSW when in forcedPWM mode, or L x ILX3MIN/(VIN - VOUT) when in pulseskipping mode.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller SVD SVC S P START CONDITION DATA LINE STABLE DATA VALID STOP CONDITION CHANGE OF DATA ALLOWED Figure 12. SVI Bus START, STOP, and Data Change Conditions DATA OUTPUT BY MASTER D7 D6 D0 NOT ACKNOWLEDGE DATA OUTPUT BY MAX17480 ACKNOWLEDGE SVC FROM MASTER 1 CLK1 2 CLK2 8 CLK8 9 CLK9 S START CONDITION ACKNOWLEDGE CLOCK PULSE Figure 13. SVI Bus Acknowledge Bus Not Busy The SVI bus is not busy when both data and clock lines remain high.
AMD 2-/3-Output Mobile Serial VID Controller SMPS Applications Information Duty-Cycle Limits Minimum Input Voltage The minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (tOFF(MIN)). The MAX17480 does not include slope compensation, so the controller becomes unstable with duty cycles greater than 50% per phase: VIN(MIN) ≥ 2VOUT(MAX) However, the controller can briefly operate with duty cycles over 50% during heavy load transients.
MAX17480 AMD 2-/3-Output Mobile Serial VID Controller Maximum Input Voltage The MAX17480 controller has a minimum on-time, which determines the maximum input operating voltage that maintains the selected switching frequency. With higher input voltages, each pulse delivers more energy than the output is sourcing to the load.
AMD 2-/3-Output Mobile Serial VID Controller plane (PGND) only at a single point directly beneath the IC. The power ground plane should connect to the high-power output ground with a short, thick metal trace from PGND to the source of the low-side MOSFETs (the middle of the star ground). 6) Connect the output power planes (VCORE, VOUT3, and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias.
LX2 Chip Information TRANSISTOR COUNT: 24,311 PROCESS: BiCMOS DH2 BST2 DL2 DL1 VDD BST1 LX1 DH1 TOP VIEW VRHOT Pin Configuration 30 29 28 27 26 25 24 23 22 21 THRM 31 20 PWRGD VCC 32 19 PGD_IN CSP1 33 18 CSP2 CSN1 34 17 CSN2 16 FBDC2 FBDC1 35 MAX17480 PGND FBAC1 36 GNDS1 37 OPTION 38 15 FBAC2 14 GNDS2 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.