Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 24 W

General Description

The MAX191 is a monolithic, CMOS, 12-bit analog-to-

digital converter (ADC) featuring differential inputs,

track/hold (T/H), internal voltage reference, internal or

external clock, and parallel or serial µP interface. The

MAX191 has a 7.5µs conversion time, a 2µs acquisition

time, and a guaranteed 100ksps sample rate.

The MAX191 operates from a single +5V supply or from

dual ±5V supplies, allowing ground-referenced bipolar

input signals. The device features a logic power-down

input, which reduces the 3mA V

supply current to

50µA max, including the internal-reference current.

Decoupling capacitors are the only external compo-

nents needed for the power supply and reference. This

ADC operates with either an external reference, or an

internal reference that features an adjustment input for

trimming system gain errors.

The MAX191 provides three interface modes: two 8-bit

parallel modes, and a serial interface mode that is com-

patible with SPI

, QSPI

, and MICROWIRE

serial-

interface standards.

________________________Applications

Battery-Powered Data Logging

PC Pen Digitizers

High-Accuracy Process Control

Electromechanical Systems

Data-Acquisition Boards for PCs

Automatic Testing Systems

Telecommunications

Digital Signal Processing (DSP)

____________________________Features

♦ 12-Bit Resolution, 1/2LSB Linearity

♦ +5V or ±5V Operation

♦ Built-In Track/Hold

♦ Internal Reference with Adjustment Capability

♦ Low Power: 3mA Operating Mode

20µA Power-Down Mode

♦ 100ksps Tested Sampling Rate

♦ Serial and 8-Bit Parallel µP Interface

♦ 24-Pin Narrow DIP and Wide SO Packages

MAX191

Low-Power, 12-Bit Sampling ADC

with Internal Reference and Power-Down

________________________________________________________________

Maxim Integrated Products

CLK/SCLK

PAR

HBEN

AIN-

AIN+

TOP VIEW

D7/DOUT

D6/SCLK

OUT

BIP

AGND

REFADJ

VREF

D5/SSTRB

D3/D11

D2/D10

DGND

D1/D9

D0/D8

BUSY

DIP/SO

MAX191

Pin Configuration

2.46V

REF

IN REF OUT

12-BIT

SAR ADC

OSC

CONTROL

LOGIC

3-STATE

OUTPUT

8-BIT

BUS

AND

SERIAL

I/O

D7/DOUT

D6/SCLK

OUT

D5/SSTRB

D3/D11

D2/D10

D1/D9

D0/D8

BUSY

HBEN

REFADJ

VREF

AIN +

AIN -

24 23

CLK/SCLK

712

22 8

AGND DGND

PAR

BIP

MAX191

Functional Diagram

19-4506; Rev 4; 2/97

PART TEMP. RANGE PIN-PACKAGE

MAX191ACNG 0°C to +70°C

24 Narrow Plastic DIP

24 Wide SO

±1/2

±1

±1/2

ERROR

(LSB)

24 Narrow Plastic DIP

MAX191BCNG

MAX191ACWG

0°C to +70°C

MAX191BCWG 0°C to +70°C 24 Wide SO ±1

MAX191BC/D Dice* ±10°C to +70°C

MAX191AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2

MAX191BENG -40°C to +85°C 24 Narrow Plastic DIP ±1

MAX191AEWG -40°C to +85°C 24 Wide SO ±1/2

MAX191AMRG 24 Narrow CERDIP** ±1/2

MAX191BMRG 24 Narrow CERDIP** ±1

-55°C to +125°C

MAX191BEWG -40°C to +85°C 24 Wide SO ±1

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

EVALUATION KIT MANUAL

FOLLOWS DATA SHEET

* Dice are specified at T

= +25°C, DC parameters only.

** Contact factory for availability and processing to MIL-STD-883.

Ordering Information

Summary of content (24 pages)

PAGE 1
9-4506; Rev 4; 2/97 ANUAL N KIT M EET IO T A U EVAL TA SH WS DA FOLLO Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down The MAX191 operates from a single +5V supply or from dual ±5V supplies, allowing ground-referenced bipolar input signals. The device features a logic power-down input, which reduces the 3mA VDD supply current to 50µA max, including the internal-reference current. Decoupling capacitors are the only external components needed for the power supply and reference.
PAGE 2
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ABSOLUTE MAXIMUM RATINGS VDD to DGND............................................................-0.3V to +7V VSS to AGND ............................................................-7V to +0.3V VDD to VSS ..............................................................................12V AGND, VREF, REFADJ to DGND................-0.3V to (VDD + 0.3V) AIN+, AIN-, PD to VSS .................................-0.3V to (VDD + 0.
PAGE 3
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.
PAGE 4
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±5%, VSS = 0V or -5V ±5%, fCLK = 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference mode, reference compensation mode—external, synchronous operation, Figure 6, T A = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V LOGIC OUTPUTS Output Low Voltage VOL IOUT = 1.
PAGE 5
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.
PAGE 6
__________________________________________Typical Operating Characteristics CLOCK FREQUENCY vs. TIMING CAPACITOR IDD 15 ISS (µA) SUPPLY CURRENT (µA) 0.1 GR191-C 20 20 1 25 GR191-B 25 GR191-A SEE FIGURE 5 TA = +25˚C CLOCK FREQUENCY (MHz) NEGATIVE SUPPLY CURRENT vs. TEMPERATURE POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE 10 VDD = +5V VSS = -5V PD = 0V 10 15 10 5 5 ISS 0 0 10 1 -60 -30 TIMING CAPACITOR (nF) 60 30 90 120 1.5 1.0 0 -60 -80 -94.3dB -96.1dB-98.0dB -93.
PAGE 7
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down PIN NAME FUNCTION 1 PD Power-Down Input. A logic low at PD deactivates the ADC—only the bandgap reference is active. A logic high selects normal operation, internal-reference compensation mode. An open-circuit condition selects normal operation, external-reference compensation mode. 2 VSS Negative Supply, 0V to -5.25V 3 AIN+ Sampled Analog Input 4 AIN- Analog Input Return.
PAGE 8
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V 3k OPEN DN DN CL CL 3k DGND DGND a. High-Z to VOH and VOL to VOH b. High-Z to VOL and VOH to VOL Figure 1. Load Circuits for Access Time +5V 3k DN DN 4.7µF 1 PD VDD CLK/SCLK 3 AIN+ PAR 4 AINHBEN 5 CS VREF MAX191 0.1µF 6 RD REFADJ 7 D7/DOUT AGND 0.
PAGE 9
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down TRACK CPACKAGE 5pF COMPARATOR CHOLD HOLD 32pF MAX191 AIN + MAX191 RIN CSWITCH 10pF CLK HOLD CLOCK CEXT AIN - +1.6V DGND 12-BIT DAC NOTE: CEXT = 120pF GENERATES 1MHz NOMINAL CLOCK Figure 4. Equivalent Input Circuit Figure 5. Internal Clock Circuit various interface modes. tection diodes are even slightly forward biased.
PAGE 10
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down CLK t17 t16 CS + RD t13 t2 tCONV BUSY t2 tCONV Figure 6. CS, RD, and CLK Synchronous Operation between 45% and 55%. Clock and Control Synchronization For best analog performance on the MAX191, the clock should be synchronized to the conversion start signals (CS and RD) as shown in Figure 6. A conversion should not be started in the 50ns before a clock edge nor in the 100ns after it.
PAGE 11
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 HBEN t8 t9 t8 t9 CS t1 t5 t1 t4 t5 RD tCONV t2 t10 t10 BUSY t11 t3 t6 OLD DATA D7–D0 DATA t7 t3 t7 NEW DATA D7–D0 NEW DATA D11–D8 t12 t12 HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High. Figure 7.
PAGE 12
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down HBEN t8 t9 t8 CLK CS t1 t4 t5 RD t2 t10 tCONV BUSY t7 t3 t3 t7 OLD DATA D7–D0 DATA NEW DATA D7–D0 t3 t7 NEW DATA D11–D8 t12 HOLD* TRACK *INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High Figure 9.
PAGE 13
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down PIN NAME D7/DOUT D6/SCLKOUT D5/SSTRB D4 D3/D11 D2/D10 D1/D9 D0/D8 D7 D6 D5 D4 D3 D2 D1 D0 Low Low Low Low D11 D10 D9 D8 DOUT SCLKOUT SSTRB Low Low Low Low Low DOUT ThreeStated ThreeStated Low Low Low Low Low HBEN = 0, PAR = 1, PARALLEL MODE HBEN = 1, PAR = 1, PARALLEL MODE HBEN = X, PAR = 0, SERIAL MODE, RD = 0 HBEN = X, PAR = 0, SERIAL MODE, RD = 1 Note: MAX191 Table 1.
PAGE 14
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down +5V 23 20 19 +5V QA SCLK 1 CS DOUT RD MAX191 SCLKOUT HBEN 18 2 17 8 QB A B 74HC164 QC QD CLOCK 21 QE QF QG SSTRB 16 9 QH CLEAR QA 1 +5V 2 8 QB A B 74HC164 QC QD CLOCK QE QF QG 9 LOGIC INPUT QH CLEAR CS SCLK SCLKOUT t19 DOUT D11 DO SSTRB NOTE: USE SSTRB TO GATE PARALLEL DATA TRANSFER FROM SHIFT REGISTER, OR TO CLEAR SHIFT REGISTERS IF DESIRED. Figure 11.
PAGE 15
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Serial-Interface Mode The serial mode is compatible with Microwire, SPI and QSPI serial interfaces. In addition, a framing signal (SSTRB) is provided that allows the devices to interface with the TMS320 family of DSPs. Set PAR low for serial mode. A falling edge on CS causes the T/H to sample the input (Figure 10). Conversion always begins on the next falling edge of SCLK, regardless of where CS occurs.
PAGE 16
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down fSCLK(MAX) = (1/2) x 1/ (tsu(M) + t22) where t su (M) is the minimum data-setup time required at the serial data input to the µP. For example, Motorola’s MC68HC11A8 data book specifies a 100ns minimum data-setup time. Using the worst case for a military grade part of t 22 = 280ns (see Timing Characteristics) and substituting in the above equation indicates a maximum SCLK frequency of 1.3MHz.
PAGE 17
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 SCLK CS DOUT HIGH-Z MSB D10 D10 D9 D9 D8 D7 D6 D4 D5 D3 D2 D1 LSB HIGH-Z a. CPOL = 0, CPHA = 0 SCLK CS DOUT HIGH-Z HIGH-Z MSB D8 D7 D6 D4 D5 D3 D2 D1 LSB b. CPOL = 1, CPHA = 1 Figure 15. QSPI Serial-Interface Timing SCLK CLKR CS SSTRB HIGH-Z DOUT HIGH-Z HIGH-Z MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB HIGH-Z Figure 16.
PAGE 18
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down Following the data transfer, the DSP receive shift register (RSR) contains a 16-bit word consisting of the 12 data bits, MSB first, followed by four trailing 0s. Applications Information Power-On Initialization When the +5V power supply is first applied to the MAX191, perform a single conversion to initialize the ADC (the BUSY signal status is undefined at power-on). Disregard the data outputs.
PAGE 19
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down fg18c MAX191 10,000 1 SUPPLY CURRENT (µA) PD 0 VREF 15µs 20µs 25µs 1000 100 RD 10 10 50 200 1k 5k 20k 100k CONVERSIONS PER SECOND Figure 18b. Low Average-Power Mode Operation (Internal Compensation) Figure 18c. Average Supply Current vs. Conversion Rate, Powering Down Between Conversions which can be achieved using power-down between conversions.
PAGE 20
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down OUTPUT CODE OPEN CIRCUIT (FLOAT) PD 0 FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 VREF 2ms RD 200ms 12.5µs FS = VREF 1LSB = FS 4096 00 . . . 011 00 . . . 010 Figure 19b. Low Average-Power Mode Operation (External Compensation) 00 . . . 001 00 . . . 000 between FFE (hex) and FFF (hex). Because interaction occurs between adjustments, offset should be adjusted before gain.
PAGE 21
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down MAX191 R7 10k MAX480 VIN AIN + R8 10k 01 . . . 111 R1 10k 01 . . . 110 MAX191 R2 100Ω VREF 00 . . . 010 D0–D11 00 . . . 001 00 . . . 000 R5 10k R6 10k R3 10k 11 . . . 111 11 . . . 110 11 . . . 101 R4 49.9Ω VREF 10 . . . 001 10 . . . 000 R9* 20k AIN 0.1µF* R10* 49.
PAGE 22
MAX191 Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down 0.01µF and 10µF bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection. If the +5V power supply is very noisy, a 10Ω resistor can be connected as a lowpass filter to filter out supply noise (Figure 23). The theoretical minimum A/D noise is caused by quantization error and is a direct result of the ADC’s resolution: SNR = (6.02n + 1.76) dB, where n is the number of bits of resolution.
PAGE 23
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down D1 V CC D2 MAX191 5V T1 602117970 (SCHOTT) 2 IN 100µF 16V IC4 OUT 74L05 14 13 5V 100µF 6V GND IC2-3 HCPL2630 (QUALITY TECHNOLOGIES) 1k 9 1k 1 8 Q1 2N3906 2 7 10 0.1µF VDD 18 IC2 TTL/CMOS OUTPUTS 24 DOUT 1k IC1 MAX250 1k 4 AIN+ 3 AIN- 4 1k 6 11 12 VIN Q2 2N3906 3 16 SSTRB 1k 1 IC5 MAX191 5 SHDN 1k 8 1 4 3 HBEN 1k 2 7 20 RD CS IC3 TTL/CMOS INPUTS 1k PAR 4 1k 5 6 EN 8 BIP 6 3 4.
PAGE 24
PD V DD CLK/SCLK PAR AINAIN+ AGND ___________________Chip Topography HBEN CS RD VREF REFADJ 0.198" (5.0292mm) AGND D7/DOUT D6/SCLK OUT D5/SSTRB D3/D11 D4 D1/D9 DGND D2/D10 D0/D8 BIP BUSY 0.142" (3.6065mm) SUBSTRATE CONNECTED TO VDD ________________________________________________________Package Information PDIPN.