Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOIC 16 W

_______________General Description

The MAX194 is a 14-bit successive-approximation ana-

log-to-digital converter (ADC) that combines high

speed, high accuracy, low power consumption, and a

10µA shutdown mode. Internal calibration circuitry cor-

rects linearity and offset errors to maintain the full rated

performance over the operating temperature range

without external adjustments. The capacitive-DAC

architecture provides an inherent 85ksps track/hold

function.

The MAX194, with an external reference (up to +5V),

offers a unipolar (0V to V

REF

) or bipolar (-V

REF

to V

REF

)

pin-selectable input range. Separate analog and digital

supplies minimize digital-noise coupling.

The chip select (CS) input controls the three-state seri-

al-data output. The output can be read either during

conversion as the bits are determined, or following con-

version at up to 5Mbps using the serial clock (SCLK).

The end-of-conversion (EOC) output can be used to

interrupt a processor, or can be connected directly to

the convert input (CONV) for continuous, full-speed

conversions.

The MAX194 is available in 16-pin DIP, wide SO, and

ceramic sidebraze packages. The output data format

provides pin-for-pin and functional compatibility with

the 16-bit MAX195 ADC.

________________________Applications

Portable Instruments Audio

Industrial Controls Robotics

Multiple Transducer Medical Signal

Measurements Acquisition

Vibrations Analysis Digital Signal

Processing

____________________________Features

♦ True 14-Bit Accuracy:

⁄

LSB INL

82dB SINAD

♦ 9.4µs Conversion Time

♦ 10µA Shutdown Mode

♦ Built-In Track/Hold

♦ AC and DC Specified

♦ Unipolar (0V to V

REF

) and Bipolar (-V

REF

to V

REF

)

Input Range

♦ Three-State Serial-Data Output

♦ Small 16-Pin DIP, SO, and Ceramic SB Packages

♦ Pin-Compatible 16-Bit Upgrade (MAX195)

______________Ordering Information

MAX194

14-Bit, 85ksps ADC with 10µA Shutdown

________________________________________________________________

Maxim Integrated Products

VDDA

VSSA

AGND

AIN

VDDD

SCLK

CLK

BP/UP/SHDN

TOP VIEW

MAX194

REF

VSSD

RESET

CONV

EOC

DGND

DOUT

DIP/Wide SO/Ceramic SB

MAX194

AIN

REF

CONV

SCLK

CLK

BP/UP/SHDN

RESET

VSSD

DGND

VDDD

VDDA

AGND

VSSA

DOUT

EOC

SAR

CONTROL LOGIC

COMPARATOR

CALIBRATION

DACs

THREE-STATE BUFFER

MAIN DAC

________________Functional Diagram

__________________Pin Configuration

19-0345; Rev 4; 12/97

PART

MAX194ACPE

MAX194BCPE

MAX194ACWE 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 Wide SO

MAX194BCWE 0°C to +70°C 16 Wide SO

MAX194AEPE -40°C to +85°C 16 Plastic DIP

MAX194BEPE -40°C to +85°C 16 Plastic DIP

MAX194AEWE -40°C to +85°C 16 Wide SO

MAX194BEWE -40°C to +85°C 16 Wide SO

MAX194AMDE -55°C to +125°C 16 Ceramic SB

MAX194BMDE -55°C to +125°C 16 Ceramic SB

EVALUATION KIT

AVAILABLE

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

Summary of content (24 pages)

PAGE 1
9-0345; Rev 4; 12/97 KIT ATION EVALU E L B AVAILA 14-Bit, 85ksps ADC with 10µA Shutdown The MAX194, with an external reference (up to +5V), offers a unipolar (0V to VREF) or bipolar (-VREF to VREF) pin-selectable input range. Separate analog and digital supplies minimize digital-noise coupling. The chip select (CS) input controls the three-state serial-data output.
PAGE 2
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown ABSOLUTE MAXIMUM RATINGS VDDD to DGND .....................................................................+7V VDDA to AGND......................................................................+7V VSSD to DGND.........................................................+0.3V to -6V VSSA to AGND .........................................................+0.3V to -6V VDDD to VDDA, VSSD to VSSA ..........................................±0.3V AIN, REF ....................
PAGE 3
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN) CLK, CS, CONV, RESET, SCLK Input High Voltage VIH VDDD = 5.25V CLK, CS, CONV, RESET, SCLK Input Low Voltage VIL VDDD = 4.75V 2.
PAGE 4
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 80 mW POWER REQUIREMENTS (cont.) Power Dissipation VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD Shutdown Supply Current (Note 5) IDDD VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V 1.
PAGE 5
14-Bit, 85ksps ADC with 10µA Shutdown PIN NAME 1 BP/UP/SHDN FUNCTION Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown. 0V = shutdown, +5V = unipolar, floating = bipolar. 2 CLK 3 SCLK Conversion Clock Input Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
PAGE 6
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown MSB LSB 32,768C 16,384C SUB-LSBs 4C 2C DUMMY C C AIN REF AGND Figure 1. Capacitor DAC Functional Diagram tCAL CLK tRCH RESET tRCS EOC CALIBRATION BEGINS CALIBRATION ENDS MAX194 OPERATION HALTS Figure 2. Initiating Calibration Calibration In an ideal DAC, each of the capacitors associated with the data bits would be exactly twice the value of the next smaller capacitor.
PAGE 7
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 tCC1 tCC2 CLK tCEL tCEH EOC * CONV tCW TRACK/HOLD tAQ CONVERSION ENDS CONVERSION BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion. If the power supplies do not settle within the MAX194’s power-on delay (500ns minimum), power-up calibration may begin with supply voltages that differ from the final values and the converter may not be properly calibrated.
PAGE 8
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown tCC1 tCC2 CLK tCEL tCEH EOC * CONV tCW tAQ TRACK/HOLD CONVERSION ENDS CONVERSION BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion. sion and EOC will go high on the following CLK falling edge (Figure 4). CONV is ignored during conversions. External Clock The conversion clock (CLK) should have a duty cycle between 25% and 75% at 1.
PAGE 9
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 START MAX194 CONV CLK START CLK CONV SEE DIGITAL INTERFACE SECTION Figure 5.
PAGE 10
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown tCONV EOC tCSS CS tCSH SCLK (CASE 1) SCLK (CASE 2) SCLK (CASE 3) B13 DOUT B12 B11 B10 B9 B1 B0 MSB tDV LSB S1 S0 SUB-LSBs tSD tDH CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0) NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE Figure 7.
PAGE 11
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 Table 1. Low-ESR Capacitor Suppliers COMPANY CAPACITOR FACTORY FAX [COUNTRY CODE] USA TELEPHONE Sprague 595D series, 592D series [1]-603-224-1430 603-224-1961 AVX TPS series [1]-207-283-1941 800-282-4975 Sanyo OS-CON series, MV-GX series [81]-7-2070-1174 619-661-6835 Nichicon PL series [1]-708-843-2798 708-843-7500 +5V BRIDGE INSTRUMENTATION AMPLIFIER VDDA MAX194 AIN REF 47µF LOW ESR 0.1µF CERAMIC Figure 9.
PAGE 12
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown +15V +5V 0.1µF 0.1µF 1k 2 VIN 16 VDDA 2k 1N914 MAX874 COMP 8 2 1000pF VOUT 6 10Ω 6 4.096V MAX427 3 12 10Ω 4 47µF GND 0.1µF 4 MAX194 0.1µF 7 0.1µF LOW ESR 0.1µF REF VSSA AGND 15 14 1N914 -15V -5V Figure 10. Typical Reference Circuit for AC Accuracy VIN ≥ 8V 2 IN MAX6241 OUT 6 12 MAX194 REF 2.2µF 3 1µF TRIM NR 5 GND 4 10k 2.2µF 0.1µF AGND 14 Figure 11.
PAGE 13
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 +5V VDDA +15V MAX194 10Ω AIN INPUT SIGNAL 1N914 DIODE CLAMPS VSSA -15V -5V Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence IN1 IN2 A0 A1 MAX194 4-TO-1 MUX IN3 IN4 AIN OUT EOC CLK CONVERSION AQUISITION EOC A0 A1 CHANGE MUX INPUT HERE Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling.
PAGE 14
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown 1k +5V +15V 1000pF 0.1µF 2 1N914 7 10Ω 6 AIN 3 MAX400 IN 100Ω 4 1N914 1.0µF 0.1µF -15V -5V Figure 14. MAX400 Drives AIN for Low-Frequency Use 1k 0.1µF 2 100pF 0.1µF 7 1N914 1 2 6 IN +5V +15V +15V 3 MAX427 1k 4 4 0.1µF -15V 10Ω 7 ELANTEC EL2003 AIN 1N914 0.0033µF 0.1µF -15V -5V Figure 15. AIN Buffer for AC/DC Use Analog Input REF and AIN Input Protection The REF and AIN signals should not exceed the MAX194 supply rails.
PAGE 15
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 510Ω +5V 0.1µF 2 7 22Ω 6 IN AIN 3 MAX410 4 0.1µF 0.01µF -5V Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing Input Acquisition and Settling Four conversion-clock periods are allocated for acquiring the input signal. At the highest conversion rate, four clock periods is 2.4µs. If more than three clock cycles have occurred since the end of the previous conversion, conversion begins on the next falling clock edge after CONV goes low.
PAGE 16
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown QSPI MAX194 PCS0 CS CONV SCK MISO CLK DOUT SCLK GPT ity provide good AC performance. AIN is diodeclamped to the ±5V rails to prevent overvoltage. The MAX427’s 15µV maximum offset voltage, 0.8µV/°C maximum drift, and less than 5nV/√Hz noise specifications make this an excellent choice for AC/DC use. If ±15V supplies are unavailable, Figure 16’s circuit works very well with the ±5V analog supplies used by the MAX194. The MAX410 has a minimum ±3.
PAGE 17
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 CS, CONV CLK EOC B13 FROM PREVIOUS CONVERSION DOUT B13 tDV B12 B0 S1 S0 B13 tDH tCD DATA LATCHED: Figure 18. Timing Diagram for Circuit of Figure 17 Data is clocked out of the MAX194 on CLK’s falling edge and can be clocked into the µP on the rising edge or the following falling edge.
PAGE 18
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown 588ns CLK START EOC CS 239ns 4.19MHz SCLK B13 DOUT 1.3µs CONVERSION TIME 9.4µs 17µs B12 B11 B1 B0 5.1µs S1 S0 4µs Figure 20. Timing Diagram for Circuit of Figure 19 Complete source code for the Motorola 68HC16 and the MAX194 evaluation kit (EV kit) using this mode is available in the MAX194 EV kit manual. Mode 2 (Asynchronous Data Transfer) This mode uses a conversion clock (CLK) and a serial clock (SCLK).
PAGE 19
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 Figure 21.
PAGE 20
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown Figure 21.
PAGE 21
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 Figure 21. MAX194 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued) Constraints on sequencing the four power supplies are as follows. • Apply VDDA before VDDD. • Apply VSSA before VSSD. • Apply AIN and REF after VDDA and VSSA are present. • The power supplies should settle within the MAX194’s power-on delay (minimum 500ns) or you should recalibrate the converter (pulse RESET low) before use.
PAGE 22
MAX194 14-Bit, 85ksps ADC with 10µA Shutdown 10Ω VDDD 0.1µF MAX194 0.1µF DGND AGND 10µF 5V 0.1µF 10µF POWER DISSIPATION (mW) VDDA 10µF 5V 10µF MAX194-FIG23 100 10 20µs WAKE-UP DELAY 0.05LSB ERROR 1 3.2µs WAKE-UP DELAY 0.1LSB ERROR 0.1 0.1µF VSSA VSSD 0.01 1 10 100 1000 10,000 100,000 CONVERSIONS PER SECOND 10Ω Figure 22. Supply Bypassing and Grounding Figure 23. Power Dissipation vs.
PAGE 23
14-Bit, 85ksps ADC with 10µA Shutdown MAX194 1/2 74HC73 MAX194 J Q CLK K +5V BP/UP/SHDN CK 2 x CLK CLOCK SHUTDOWN CK (2 x CLK) Q (CLK) J (CLOCK SHUTDOWN) Figure 24. Circuit to Stop Free-Running Asynchronous CLK Total Harmonic Distortion SIGNAL AMPLITUDE (dB) -10 fIN = 1kHz fS = 85kHz TA = +25°C -30 -50 -70 -90 -110 -130 -150 0 5 10 15 20 25 30 35 40 FREQUENCY (kHz) Figure 25. MAX194 FFT Plot measure of the ADC’s usefulness.
PAGE 24
13.5 MAX194-27 90 MAX194-26 14.0 fS = 85kHz TA = +25°C 85 13.0 12.5 SINAD (dB) EFFECTIVE BITS MAX194 14-Bit, 85ksps ADC with 10µA Shutdown 12.0 11.5 fS = 85kHz TA = +25°C 80 75 70 11.0 65 10.5 10.0 0.1 60 1 10 100 0.1 INPUT FREQUENCY (kHz) 10 1 100 FREQUENCY (kHz) Figure 26. Effective Bits vs. Input Frequency Figure 27. Signal-to-Noise + Distortion vs. Frequency 11 . . . 111 11 . . . 110 11 . . . 101 11 . . . 111 11 . . . 110 11 . . . 101 11 . . . 100 11 . . . 011 11 . . .