9-0377; Rev 1; 12/97 KIT ATION EVALU E L B AVAILA 16-Bit, 85ksps ADC with 10µA Shutdown The chip select (CS) input controls the three-state serialdata output. The output can be read either during conversion as the bits are determined, or following conversion at up to 5Mbps using the serial clock (SCLK). The end-ofconversion (EOC) output can be used to interrupt a processor, or can be connected directly to the convert input (CONV) for continuous, full-speed conversions.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ABSOLUTE MAXIMUM RATINGS VDDD to DGND .....................................................................+7V VDDA to AGND......................................................................+7V VSSD to DGND.........................................................+0.3V to -6V VSSA to AGND .........................................................+0.3V to -6V VDDD to VDDA, VSSD to VSSA ..........................................±0.3V AIN, REF ....................
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN) CLK, CS, CONV, RESET, SCLK Input High Voltage VIH VDDD = 5.25V CLK, CS, CONV, RESET, SCLK Input Low Voltage VIL VDDD = 4.75V 2.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown ELECTRICAL CHARACTERISTICS (continued) (VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK = 1.7MHz, VREF = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 80 mW POWER REQUIREMENTS (cont.) Power Dissipation VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V VDDD Shutdown Supply Current (Note 5) IDDD VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V, BP/UP/SHDN = 0V 1.
16-Bit, 85ksps ADC with 10µA Shutdown PIN NAME 1 BP/UP/SHDN FUNCTION Bipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown. 0V = shutdown, +5V = unipolar, floating = bipolar. 2 CLK 3 SCLK Conversion Clock Input Serial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown MSB LSB 32,768C 16,384C 4C 2C DUMMY C C AIN REF AGND Figure 1. Capacitor DAC Functional Diagram tCAL CLK tRCH tRCS RESET EOC CALIBRATION BEGINS CALIBRATION ENDS MAX195 OPERATION HALTS Figure 2. Initiating Calibration Calibration In an ideal DAC, each of the capacitors associated with the data bits would be exactly twice the value of the next smaller capacitor.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 tCC1 tCC2 CLK tCEL tCEH EOC * CONV tCW TRACK/HOLD tAQ CONVERSION ENDS CONVERSION BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion. If the power supplies do not settle within the MAX195’s power-on delay (500ns minimum), power-up calibration may begin with supply voltages that differ from the final values and the converter may not be properly calibrated.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown tCC1 tCC2 CLK tCEL tCEH EOC * CONV tCW tAQ TRACK/HOLD CONVERSION ENDS CONVERSION BEGINS * THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion. after the end of the previous conversion and EOC will go high on the following CLK falling edge (Figure 4). External Clock The conversion clock (CLK) should have a duty cycle between 25% and 75% at 1.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 START MAX195 CONV CLK START CLK CONV SEE DIGITAL INTERFACE SECTION Figure 5.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown tCONV EOC tCSS CS tCSH SCLK (CASE 1) SCLK (CASE 2) SCLK (CASE 3) B15 DOUT B14 B13 B12 B11 MSB tDV B3 B2 B1 B0 LSB tSD tDH CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0) CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1) CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0) NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE Figure 7.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 Table 1. Low-ESR Capacitor Suppliers COMPANY CAPACITOR FACTORY FAX [COUNTRY CODE] USA TELEPHONE Sprague 595D series, 592D series 1-603-224-1430 603-224-1961 AVX TPS series 1-207-283-1941 800-282-4975 Sanyo OS-CON series, MVGX series 81-7-2070-1174 619-661-6835 Nichicon PL series 1-708-843-2798 708-843-7500 +5V BRIDGE INSTRUMENTATION AMPLIFIER VDDA AIN MAX195 REF 47µF LOW ESR 0.1µF CERAMIC AGND Figure 9.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown +15V +5V 0.1µF 2 0.1µF 1k VIN 16 VDDA 2k COMP 2 MAX874 6 0.1µF 7 1000pF VOUT 1N914 8 4.096V 3 12 MAX427 REF 10Ω 47µF LOW ESR 4 0.1µF GND MAX195 10Ω 6 0.1µF 1N914 VSSA AGND 15 14 0.1µF 4 -15V -5V Figure 10. Typical Reference Circuit for AC Accuracy VIN ≥ 8V 2 IN MAX6241 OUT 12 6 MAX195 REF 2.2µF 3 1µF TRIM NR 5 GND 4 10k 2.2µF 0.1µF AGND 14 Figure 11.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 +5V +15V VDDA MAX195 10Ω AIN INPUT SIGNAL 1N914 DIODE CLAMPS VSSA -15V -5V Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence REF and AIN Input Protection The REF and AIN signals should not exceed the MAX195 supply rails. If this can occur, diode clamp the signal to the supply rails. Use silicon diodes and a 10Ω current-limiting resistor (Figures 10 and 12) or Schottky diodes without the resistor.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown IN1 IN2 A0 A1 MAX195 4-TO-1 MUX IN3 AIN OUT IN4 EOC CLK CONVERSION ACQUISITION EOC A0 A1 CHANGE MUX INPUT HERE Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling. 1k +5V +15V 0.1µF 2 1000pF 1N914 7 10Ω 6 IN AIN 3 MAX400 100Ω 4 1N914 0.1µF -15V 1.0µF -5V Figure 14.
16-Bit, 85ksps ADC with 10µA Shutdown ing. Also, to reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest (Figures 14, 15, 16). DC Accuracy If DC accuracy is important, choose a buffer with an offset much less than the MAX195’s maximum offset (±3LSB = ±366µV for a ±4V input range), or whose offset can be trimmed while maintaining good stability over the required temperature range.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown If ±15V supplies are unavailable, Figure 16’s circuit works very well with the ±5V analog supplies used by the MAX195. The MAX410 has a minimum ±3.5V common-mode input range, with a similar output voltage swing, which allows use of a reference voltage up to 3.5V. The offset voltage (250µV) is about 2LSB. The drift (1µV/°C), unity-gain bandwidth (28MHz), and low voltage noise (2.4nV/√Hz) are appropriate for 16-bit performance. 510Ω +5V 0.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 CS, CONV CLK EOC B15 FROM PREVIOUS CONVERSION DOUT B15 tDV B14 B2 B1 B0 B15 tDH tCD DATA LATCHED: Figure 18. Timing Diagram for Circuit of Figure 17 (Mode 1) If clocking data in on the falling edge (CPOL = 0, CPHA = 1), the maximum CLK rate is given by: 1 fCLK(max) = t CD + t SD QSPI PCS0 GPT Do not exceed the maximum CLK frequency given in the Electrical Characteristics table.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown 588ns CLK START EOC CS 239ns 4.19MHz SCLK B15 DOUT 1.3µs CONVERSION TIME 9.4µs 17µs* B14 B13 B3 B2 5.1µs B1 B0 4µs * INTERRUPT LATENCY OF THE PROCESSOR Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2) An OR gate is used to synchronize the “start” signal to the asynchronous CLK, as described in the External Clock section.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 Figure 21.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Figure 21.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 Figure 21. MAX195 Code Listing for 68HC16 Module and Circuit of Figure 19 (continued) Be sure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05Ω creates an error voltage of about 250µV, or about 2LSBs error with a ±4V full-scale system.
MAX195 16-Bit, 85ksps ADC with 10µA Shutdown 10Ω VDDD 0.1µF MAX195 0.1µF 10µF DGND AGND 10µF 5V 0.1µF 10µF POWER DISSIPATION (mW) 5V MAX195-FIG23 100 50µs WAKE-UP DELAY 0.01LSB ERROR VDDA 10µF 10 20µs WAKE-UP DELAY 0.25LSB ERROR 1 0.1 3.2µs WAKE-UP DELAY 0.5LSB ERROR 0.1µF VSSA 0.01 1 VSSD 10 100 1000 10,000 100,000 CONVERSIONS PER SECOND 10Ω Figure 22. Supply Bypassing and Grounding Figure 23. Power Dissipation vs.
16-Bit, 85ksps ADC with 10µA Shutdown MAX195 1/2 74HC73 MAX195 CLOCK SHUTDOWN J +5V K Q CLK BP/UP/SHDN CK 2 x CLK CK (2 x CLK) Q (CLK) J (CLOCK SHUTDOWN) Figure 24. Circuit to Stop Free-Running Asynchronous CLK SIGNAL AMPLITUDE (dB) -10 fIN = 1kHz fS = 85kHz TA = +25°C -30 -50 -70 -90 -110 -130 -150 0 5 10 15 20 25 FREQUENCY (kHz) Figure 25. MAX195 FFT Plot 30 35 40 Even better than oversampling and averaging is oversampling and digital filtering.
fS = 85kHz TA = +25°C 15 100 MAX195-26 16 MAX195-28 MAX195 16-Bit, 85ksps ADC with 10µA Shutdown fS = 85kHz TA = +25°C 95 SINAD (dB) EFFECTIVE BITS 90 14 13 12 85 80 75 70 11 65 10 0.1 60 1 10 100 0.1 FREQUENCY (kHz) 100 This is expressed as follows: 18 16 IDEAL CONVERSION 14 VREF = +4.5V VAIN = +2.25V UNIPOLAR MODE 85ksps MAX195 FG27 OCCURRENCES OF OUTPUT CODE (THOUSANDS) 10 Figure 28. Signal-to-Noise + Distortion vs. Frequency Figure 26. Effective Bits vs.
16-Bit, 85ksps ADC with 10µA Shutdown 11 . . . 111 11 . . . 110 11 . . . 101 11 . . . 100 11 . . . 011 11 . . . 010 BP/UP/SHDN VSSA CLK VDDA SCLK AGND 00 . . . 110 00 . . . 101 00 . . . 100 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 AIN REF VREF - (1LSB) 0V 0.273" (6.93mm) VDDD Figure 29. MAX195 Unipolar Transfer Function DOUT 11 . . . 111 11 . . . 110 11 . . . 101 DGND VSSD EOC 10 . . . 010 10 . . . 001 10 . . . 000 01 . . . 111 01 . . . 110 CS CONV RESET 0.144" (3.
________________________________________________________Package Information PDIPN.
16-Bit, 85ksps ADC with 10µA Shutdown SOICW.
___________________________________________Package Information (continued) SBN.EPS MAX195 16-Bit, 85ksps ADC with 10µA Shutdown Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
