9-3867; Rev 0; 10/05 KIT ATION EVALU E L B A AVAIL 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End WiMAX is a service mark of Bandwidth.com, Inc. Ordering Information PART* MAX19706ETM PIN-PACKAGE PKG CODE 48 Thin QFN-EP** T4877-4 MAX19706ETM+ 48 Thin QFN-EP** T4877-4 *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. ♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging Mode ♦ Excellent Gain/Phase Match ±0.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND......................-0.3V to VDD ADC1, ADC2 to GND .................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND ............-0.3V to (VDD + 0.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) 55.0 54.5 53.0 52.5 52.0 51.5 51.0 50.5 50.0 -70 -80 -90 -100 0 1 2 3 4 5 6 7 8 0 9 10 -64 Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE QA fIN = 5.468363MHz 55.5 QA -72 -73 IA 54.5 THD (dB) SINAD (dB) 54.5 fIN = 5.468363MHz -71 55.0 55.0 SNR (dB) -70 XMAX19706 toc14 fIN = 5.468363MHz 55.5 56.0 XMAX19706 toc13 56.0 Rx ADC TOTAL HARMONIC DISTORTION vs. SAMPLING RATE MAX19706 toc15 Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE IA IA -74 -75 -76 54.0 54.0 53.5 53.5 53.0 53.0 QA -77 -78 -79 4.0 6.
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE 85 81 82 1.4 1.0 IA 0.8 77 SFDR (dBc) 1.2 SFDR (dBc) GAIN ERROR (%FS) 1.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End 0.8 0.6 0.6 0.4 0.2 0.2 0.2 0 -0.2 INL (LSB) 0.4 DNL (LSB) 0.4 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 -1.0 128 256 384 512 640 768 896 1024 128 256 384 512 640 768 896 1024 0 DIGITAL OUTPUT CODE 0.520 MAX19706 toc34 0.4 0.3 128 256 384 512 640 768 896 1024 DIGITAL INPUT CODE REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE Tx DAC DIFFERENTIAL NONLINEARITY 0.
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT STEP FROM 1/4FS TO 3/4FS MAX19706 toc39 2.0 MAX19706 toc38 MAX19706 toc37 2.5 1.5 1.0 2.0 0.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End PIN NAME 10 QAP FUNCTION 13–18, 21–24 D0–D9 Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). 19 OGND Output-Driver Ground 20 OVDD Output-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 25 SHDN Active-Low Shutdown Input.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Dual, 10-Bit Rx ADC VREF is the difference between VREFP and VREFN. See the Reference Configurations section for details. The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D0–D9) VREF x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023 VREF x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022 VREF x 1/512 +1 10 0000 0001 513 VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512 -VREF x 1/512 -1 01 1111 1111 511 -VREF x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1 -VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0 1 LSB = 2 x VREF 1
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End 5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI) CHI CHQ tCLK tCL tCH CLK tDOQ D0–D9 tDOI D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q Figure 3. Rx ADC System Timing Diagram Dual, 10-Bit Tx DAC The dual, 10-bit digital-to-analog converter (Tx DAC) operates with clock speeds up to 22MHz. The Tx DAC digital inputs, D0–D9, are multiplexed on a single 10-bit bus.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End used to optimize sideband and carrier suppression in the Tx signal path (see Table 9). MAX19706 EXAMPLE: Tx DAC I-CH Tx RFIC INPUT REQUIREMENTS • DC COMMON-MODE BIAS = 1.2V (MIN), 1.5V (MAX) 0 90 Tx DAC Q-CH • BASEBAND INPUT = ±400mV DC-COUPLED FULL SCALE = 1.55V VCOM = 1.35V COMMON-MODE LEVEL SELECT CM1 = 0, CM0 = 0 VCOM = 1.35V VDIFF = ±400mV ZERO SCALE = 1.15V 0V Figure 4.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I channel (ID) is latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal. composed of A3–A0 control bits and D11–D0 data bits. Data is shifted in MSB first (D11) and LSB last (A0).
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End D11 REGISTER NAME (MSB) E11 = 0 ENABLE-16 Reserved D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB) E10 = 0 Reserved E9 — — E6 E5 E4 E3 E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode) ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 T/R STATE PIN 27 0 Ext1-Rx 0011 COMMENT Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1. Low Power: Slow Tx to Rx when T/R transitions 1 to 0.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End MAX19706 Table 6. Tx-Rx Control Using SPI Commands ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 1011 0000 (16-Bit Mode) or 1000 (8-Bit Mode) 1100 1101 1110 T/R MODE PIN 27 X X X X FUNCTION (Tx-Rx SWITCHING SPEED) SPI1-Rx SPI2-Tx SPI3-Rx SPI4-Tx DESCRIPTION COMMENTS SLOW Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Low Power: Slow Rx to Tx through SPI command.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Table 9.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Tx-Rx control, program the MAX19706 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface. When using SPI commands exclusively to control Tx-Rx states (external T/R pin is not used), then the T/R pin must be pulled up to OVDD or pulled down to OGND.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Mode-Recovery Timing Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200kΩ. If capacitive loading exceeds 5pF, then add a 10kΩ resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK).
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End MAX19706 Table 17. Reference Modes VREFIN REFERENCE MODE > 0.8V x VDD Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Using Op-Amp Coupling IDP VOUT MAX19706 IDN QDP VOUT QDN Figure 9. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC Drive the MAX19706 Rx ADC with op amps when a balun transformer is not available. Figures 10 and 11 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End MAX19706 R5 600Ω R4 600Ω RISO 22Ω R1 600Ω IAN CIN 5pF MAX19706 R2 600Ω R3 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM RISO 22Ω CIN 5pF IAP R11 600Ω R10 600Ω Figure 11. Rx ADC DC-Coupled Differential Drive 10-BIT ADC Rx-I 802.
Grounding, Bypassing, and Board Layout The MAX19706 requires high-speed board layout design techniques. Refer to the MAX19707 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Signal-to-Noise and Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. ADC Dynamic Parameter Definitions Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only.
MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End VDD = +2.7V TO +3.3V IAP OVDD = +1.8V TO +3.3V 10-BIT ADC IAN MAX19706 SHDN T/R QAP 10-BIT ADC QAN HALFDUPLEX BUS IDP D0–D9 10-BIT DAC IDN QDP 10-BIT DAC QDN PROGRAMMABLE OFFSET/CM DAC1 12-BIT DAC DAC2 12-BIT DAC DAC3 12-BIT DAC SYSTEM CLOCK CLK SERIAL INTERFACE AND SYSTEM CONTROL DIN SCLK CS 1.
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX19706 10-Bit, 22Msps, Ultra-Low-Power Analog Front-End (NE-1) X e E/2 k e D/2 CL (ND-1) X e D D2 D2/2 b L E2/2 DETAIL B e E2 CL L L1 CL k CL L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.
10-Bit, 22Msps, Ultra-Low-Power Analog Front-End PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
