Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit TQFN 48

General Description

The MAX19707 is an ultra-low-power, mixed-signal ana-

log front-end (AFE) designed for power-sensitive com-

munication equipment. Optimized for high dynamic

performance at ultra-low power, the device integrates a

dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit,

45Msps transmit (Tx) DAC; three fast-settling 12-bit

aux-DAC channels for ancillary RF front-end control;

and a 10-bit, 333ksps housekeeping aux-ADC. The typ-

ical operating power in Tx-Rx FAST mode is 84.6mW at

a 45MHz clock frequency.

The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR

at f

= 5.5MHz and f

CLK

= 45MHz. The analog I/Q

input amplifiers are fully differential and accept

1.024V

P-P

full-scale signals. Typical I/Q channel match-

ing is ±0.03° phase and ±0.01dB gain.

The Tx DACs feature 73.2dBc SFDR at f

OUT

= 2.2MHz

and f

CLK

= 45MHz. The analog I/Q full-scale output volt-

age is ±400mV differential. The Tx DAC common-mode

DC level is programmable from 0.71V to 1.05V. The I/Q

channel offset is programmable to optimize radio lineup

sideband/carrier suppresion. The typical I/Q channel

matching is ±0.01dB gain and ±0.07° phase.

The Rx ADC and Tx DAC share a single, 10-bit parallel,

high-speed digital bus allowing half-duplex operation

for time-division duplex (TDD) applications. A 3-wire

serial interface controls power-management modes, the

aux-DAC channels, and the aux-ADC channels.

The MAX19707 operates on a single 2.7V to 3.3V ana-

log supply and 1.8V to 3.3V digital I/O supply. The

MAX19707 is specified for the extended (-40°C to

+85°C) temperature range and is available in a 48-pin,

thin QFN package. The Selector Guide at the end of the

data sheet lists other pin-compatible versions in this

AFE family.

Applications

Features

♦ Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit,

45Msps Tx DAC

♦ Ultra-Low Power

84.6mW at f

CLK

= 45MHz, Fast Mode

77.1mW at f

CLK

= 45MHz, Slow Mode

Low-Current Standby and Shutdown Modes

♦ Programmable Tx DAC Common-Mode DC Level

and I/Q Offset Trim

♦ Excellent Dynamic Performance

SNR = 54.2dB at f

= 5.5MHz (Rx ADC)

SFDR = 73.2dBc at f

OUT

= 2.2MHz (Tx DAC)

♦ Three 12-Bit, 1µs Aux-DACs

♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and

Data Averaging

♦ Excellent Gain/Phase Match

±0.03° Phase, ±0.01dB Gain (Rx ADC) at

= 5.5MHz

♦ Multiplexed Parallel Digital I/O

♦ Serial-Interface Control

♦ Versatile Power-Control Circuits

Shutdown, Standby, Idle, Tx/Rx Disable

♦ Miniature 48-Pin Thin QFN Package

(7mm x 7mm x 0.8mm)

MAX19707

10-Bit, 45Msps, Ultra-Low-Power

Analog Front-End

________________________________________________________________ Maxim Integrated Products 1

19-3826; Rev 1; 6/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Ordering Information

PART*

PIN-PACKAGE

PKG CODE

MAX19707ETM

48 Thin QFN-EP**

T4877-4

MAX19707ETM+

48 Thin QFN-EP**

T4877-4

*All devices are specified over the -40°C to +85°C operating

range.

**EP = Exposed paddle.

+Denotes lead-free package.

Functional Diagram and Selector Guide appear at end of

data sheet.

OGND

IDN

IDP

GND

QDN

QDP

REFN

EXPOSED PADDLE (GND)

REFIN

DAC1

COM

DAC2

1234

ADC1

ADC2

GND

SCLK

DIN

T/R

SHDN

DOUT

DAC3

THIN QFN

MAX19707

TOP VIEW

REFP

IAP

IAN

GND

CLK

GND

QAN

QAP

GND

36 35 34 33

31 30

29 28

27 26

Pin Configuration

WiMAX CPEs

802.11a/b/g WLAN

VoIP Terminals

Portable Communication

Equipment

Summary of content (37 pages)

PAGE 1
9-3826; Rev 1; 6/07 KIT ATION EVALU LE B A IL A AV 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Portable Communication Equipment Ordering Information PART* PIN-PACKAGE PKG CODE MAX19707ETM 48 Thin QFN-EP** T4877-4 MAX19707ETM+ 48 Thin QFN-EP** T4877-4 *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package.
PAGE 2
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND-0.3V to (VDD + 0.3V)D0–D9, DOUT, T/R, SHDN, SCLK, DIN, CS, CLK to OGND ......
PAGE 3
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 4
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 5
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 6
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 7
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 8
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 9
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.
PAGE 10
Typical Operating Characteristics (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -40 -50 -60 -70 0 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 0 2.5 5.0 7.
PAGE 11
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End QA -40 50 Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE fIN = 12.4980346MHz 75 -45 MAX19707 toc12 fIN = 13.00155MHz MAX19707 toc10 60 Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT AMPLITUDE MAX19707 toc11 Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE fIN = 12.
PAGE 12
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -60 QA 85 80 -70 -75 -80 IA 75 70 0.4 0.2 0 -0.2 -0.4 QA -0.6 -0.8 -95 60 45 55 65 -1.
PAGE 13
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Rx ADC INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.8 0.6 IVDD 22 20 18 16 10 15 20 25 30 35 40 -0.2 -0.2 -0.6 -0.3 -0.8 -0.4 -1.0 -0.5 0 45 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Tx DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE MAX19707 toc31 0.5 0.4 0.3 0.1 0 -0.2 0 -0.1 -0.4 -0.2 -0.6 -0.3 -0.8 -0.4 -1.0 0.510 0.505 0.500 -0.
PAGE 14
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) AUX-DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE AUX-DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0.6 0.4 0.5 0.2 DNL (LSB) 1.0 0 -0.
PAGE 15
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End PIN NAME 10 QAP FUNCTION 13–18, 21–24 D0–D9 Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). 19 OGND Output-Driver Ground 20 OVDD Output-Driver Power Supply. Supply range from 1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 25 SHDN Active-Low Shutdown Input.
PAGE 16
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Dual, 10-Bit Rx ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA.
PAGE 17
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D0–D9) VREF x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023 VREF x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022 VREF x 1/512 +1 10 0000 0001 513 VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512 -VREF x 1/512 -1 01 1111 1111 511 -VREF x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1 -VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0 2 x VREF 1024 VREF
PAGE 18
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End 5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI) CHI CHQ tCLK tCL tCH CLK tDOQ D0–D9 tDOI D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q Figure 3. Rx ADC System Timing Diagram Dual, 10-Bit Tx DAC The dual, 10-bit digital-to-analog converter (Tx DAC) operates with clock speeds up to 45MHz. The Tx DAC digital inputs, D0–D9, are multiplexed on a single 10-bit bus.
PAGE 19
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End used to optimize sideband and carrier suppression in the Tx signal path (see Table 9). MAX19707 EXAMPLE: Tx DAC I-CH Tx RFIC INPUT REQUIREMENTS • DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (MAX) 0 90 Tx DAC Q-CH • BASEBAND INPUT = ±400mV DC-COUPLED FULL SCALE = 1.25V VCOM = 1.05V COMMON-MODE LEVEL SELECT CM1 = 0, CM0 = 0 VCOM = 1.05V VDIFF = ±400mV ZERO SCALE = 0.85V 0V Figure 4.
PAGE 20
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End composed of A3–A0 control bits and D11–D0 data bits. Data is shifted in MSB first (D11) and LSB last (A0). Tables 4, 5, and 6 show the MAX19707 operating modes and SPI commands. The serial interface remains active in all modes. Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs.
PAGE 21
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB) ENABLE-16 E11 = 0 Reserved E10 = 0 Reserved E9 — — E6 E5 E4 E3 E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3
PAGE 22
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode) ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 T/R STATE PIN 27 0 Ext1-Rx 0011 COMMENT Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1. Low Power: Slow Tx to Rx when T/R transitions 1 to 0.
PAGE 23
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 Table 6. Tx-Rx Control Using SPI Commands ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 1011 0000 (16-Bit Mode) or 1000 (8-Bit Mode) 1100 1101 1110 T/R MODE PIN 27 X X X X FUNCTION (Tx-Rx SWITCHING SPEED) SPI1-Rx SPI2-Tx SPI3-Rx SPI4-Tx DESCRIPTION COMMENTS SLOW Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Low Power: Slow Rx to Tx through SPI command.
PAGE 24
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Table 9.
PAGE 25
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End mode, use the T/R input (pin 27) to switch between Rx and Tx modes. Using the T/R pin provides faster switching between Rx and Tx modes. To override the external Tx-Rx control, program the MAX19707 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface.
PAGE 26
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Mode-Recovery Timing Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error.
PAGE 27
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200kΩ. If capacitive loading exceeds 5pF, then add a 10kΩ resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time.
PAGE 28
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK).
PAGE 29
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 Table 17. Reference Modes VREFIN REFERENCE MODE > 0.8V x VDD Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
PAGE 30
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Using Op-Amp Coupling IDP VOUT MAX19707 IDN QDP VOUT QDN Figure 9. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC Drive the MAX19707 Rx ADC with op amps when a balun transformer is not available. Figures 10 and 11 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications.
PAGE 31
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 R4 600Ω R5 600Ω RISO 22Ω R1 600Ω IAN CIN 5pF MAX19707 R2 600Ω R3 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM RISO 22Ω CIN 5pF IAP R11 600Ω R10 600Ω Figure 11. Rx ADC DC-Coupled Differential Drive 10-BIT ADC Rx-I 802.
PAGE 32
Grounding, Bypassing, and Board Layout The MAX19707 requires high-speed board layout design techniques. Refer to the MAX19707 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.
PAGE 33
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. ADC Dynamic Parameter Definitions Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only.
PAGE 34
MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB.
PAGE 35
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End VDD = 2.7V TO 3.3V IAP OVDD = 1.8V TO 3.3V 10-BIT ADC IAN MAX19707 SHDN T/R QAP 10-BIT ADC QAN HALFDUPLEX BUS IDP D0–D9 10-BIT DAC IDN QDP 10-BIT DAC QDN PROGRAMMABLE OFFSET/CM DAC1 12-BIT DAC DAC2 12-BIT DAC DAC3 12-BIT DAC SYSTEM CLOCK CLK SERIAL INTERFACE AND SYSTEM CONTROL DIN SCLK CS 1.
PAGE 36
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (NE-1) X e E/2 k e D/2 C L (ND-1) X e D D2 D2/2 b L E2/2 C L k E2 C L C L L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.
PAGE 37
10-Bit, 45Msps, Ultra-Low-Power Analog Front-End PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 F 2 2 Revision History Pages changed at Rev 1: 1, 4, 6, 7, 10–15, 17, 33, 35, 36, 37 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.