Datasheet

MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈ 10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS
Receive Transmit Isolation
ADC f
INI
= f
INQ
= 5.5MHz, DAC f
OUTI
=
f
OUTQ
= 2.2MHz, f
CLK
= 45MHz
85 dB
AUXILIARY ADC (ADC1, ADC2)
Resolution N 10 Bits
AD1 = 0 (default)
2.048
Full-Scale Reference V
REF
AD1 = 1
V
DD
V
Analog Input Range
0 to
V
REF
V
Analog Input Impedance At DC
500
kΩ
Input-Leakage Current
Measured at unselected input from 0 to
V
REF
±0.1
µA
Gain Error GE Includes reference error -5 +5
%FS
Zero-Code Error ZE 2 mV
Differential Nonlinearity DNL
±0.53
LSB
Integral Nonlinearity INL
±0.45
LSB
Supply Current
210
µA
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution N (Note 6) 12 Bits
Integral Nonlinearity INL
±1.25
LSB
Differential Nonlinearity DNL
Guaranteed monotonic over codes 100 to
4000 (Note 6)
-1.0 ±0.65 +1.1
LSB
Gain Error GE R
L
> 200kΩ
±0.7
%FS
Zero-Code Error ZE
±0.6
%FS
Output-Voltage Low V
OL
R
L
> 200kΩ
0.1 V
Output-Voltage High V
OH
R
L
> 200kΩ
2.56
V
DC Output Impedance DC output at midscale 4 Ω
Settling Time From 1/4 FS to 3/4 FS, within ±10 LSB 1 µs
Glitch Impulse From 0 to FS transition 24
nV•s
Rx ADC–Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
t
DOI
Figure 3 (Note 6) 5.4 6.5 8.1 ns
CLK Fall to Channel-Q Output
Data Valid
t
DOQ
Figure 3 (Note 6) 7.3 8.8
11.1
ns
I-DAC DATA to CLK Fall Setup
Time
t
DSI
Figure 5 (Note 6) 9 ns