Datasheet
MAX19707
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈ 10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33µF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Q-DAC DATA to CLK Rise Setup
Time
t
DSQ
Figure 5 (Note 6) 9 ns
CLK Fall to I-DAC Data Hold Time
t
DHI
Figure 5 (Note 6) -4 ns
CLK Rise to Q-DAC Data Hold
Time
t
DHQ
Figure 5 (Note 6) -4 ns
CLK Duty Cycle 50 %
CLK Duty-Cycle Variation
±15
%
Digital Output Rise/Fall Time 20% to 80% 2.6 ns
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6)
Falling Edge of CS to Rising Edge
of First SCLK Time
t
CSS
10 ns
DIN to SCLK Setup Time t
DS
10 ns
DIN to SCLK Hold Time t
DH
0ns
SCLK Pulse-Width High t
CH
25 ns
SCLK Pulse-Width Low t
CL
25 ns
SCLK Period t
CP
50 ns
SCLK to CS Setup Time t
CS
10 ns
CS High Pulse Width t
CSW
80 ns
CS High to DOUT Active High t
CSD
Bit AD0 set
200
ns
CS High to DOUT Low (Aux-ADC
Conversion Time)
t
CONV
Bit AD0 set, no averaging (see Table 14),
f
CLK
= 45MHz,
CLK divider = 16 (see Table 15)
4.27
µs
DOUT Low to CS Setup Time t
DCS
Bit AD0, AD10 set
200
ns
SCLK Low to DOUT Data Out t
CD
Bit AD0, AD10 set
14.5
ns
CS High to DOUT High Impedance
t
CHZ
Bit AD0, AD10 set
200
ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
85.2
Shutdown Wake-Up Time
t
WAKE
,
SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
28.2
µs
Fr om i d l e to Rx m od e w i th C LK p r esent
d ur i ng i d l e, AD C settl es to w i thi n 1d B S IN AD
9.8
Idle Wake-Up Time (With CLK)
t
WAKE
,
ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
6.4
µs
From standby to Rx mode, ADC settles to
within 1dB SINAD
13.7
Standby Wake-Up Time
t
WAKE
,
ST1
From standby to Tx mode, DAC settles to
10 LSB error
24
µs