Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit TQFN EP 56

General Description

The MAX19713 is an ultra-low-power, highly integrated

mixed-signal analog front-end (AFE) ideal for wideband

communication applications operating in full-duplex (FD)

mode. Optimized for high dynamic performance and

ultra-low power, the device integrates a dual 10-bit,

45Msps receive (Rx) ADC; dual 10-bit, 45Msps transmit

(Tx) DAC; three fast-settling 12-bit aux-DAC channels for

ancillary RF front-end control; and a 10-bit, 333ksps

housekeeping aux-ADC. The typical operating power in

FD mode is 91.8mW at a 45MHz clock frequency.

The Rx ADCs feature 54dB SINAD and 72.2dBc SFDR at

5.5MHz input frequency with a 45MHz clock frequency.

The analog I/Q input amplifiers are fully differential and

accept 1.024V

P-P

full-scale signals. Typical I/Q channel

matching is ±0.03 phase and ±0.02dB gain.

The Tx DACs feature 70.3dBc SFDR at f

OUT

= 2.2MHz

and f

CLK

= 45MHz. The analog I/Q full-scale output volt-

age range is ±400mV differential. The output DC com-

mon-mode voltage is selectable from 0.71V to 1.06V. The

I/Q channel offset is adjustable to optimize radio lineup

sideband/carrier suppression. Typical I/Q channel

matching is ±0.01dB gain and ±0.05° phase.

Two independent 10-bit parallel, high-speed digital

buses used by the Rx ADC and Tx DAC allow full-

duplex operation for frequency-division duplex applica-

tions. The Rx ADC and Tx DAC can be disabled

independently to optimize power management. A 3-wire

serial interface controls power-management modes, the

aux-DAC channels, and the aux-ADC channels.

The MAX19713 operates on a single 2.7V to 3.3V analog

supply and 1.8V to 3.3V digital I/O supply. The

MAX19713 is specified for the extended (-40°C to

+85°C) temperature range and is available in a 56-pin,

thin QFN package. The

Selector Guide

at the end of the

data sheet lists other pin-compatible versions in this AFE

family. For time-division duplex (TDD) applications, refer

to the MAX19705–MAX19708 AFE family of products.

Applications

Features

♦ Dual 10-Bit, 45Msps Rx ADC and Dual 10-Bit,

45Msps Tx DAC

♦ Ultra-Low Power

91.8mW at f

CLK

= 45MHz, FD Mode

79.2mW at f

CLK

= 45MHz, Slow Rx Mode

49.5mW at f

CLK

= 45MHz, Slow Tx Mode

Low-Current Standby and Shutdown Modes

♦ Programmable Tx DAC Common-Mode DC Level

and I/Q Offset Trim

♦ Excellent Dynamic Performance

SNR = 54.1dB at f

= 5.5MHz (Rx ADC)

SFDR = 70.3dBc at f

OUT

= 2.2MHz (Tx DAC)

♦ Three 12-Bit, 1µs Aux-DACs

♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and

Data Averaging

♦ Excellent Gain/Phase Match

±0.03° Phase, ±0.02dB Gain (Rx ADC) at

= 5.5MHz

♦ Multiplexed Parallel Digital I/O

♦ Serial-Interface Control

♦ Versatile Power-Control Circuits

Shutdown, Standby, Idle, Tx/Rx Disable

♦ Miniature 56-Pin Thin QFN Package

(7mm x 7mm x 0.8mm)

MAX19713

10-Bit, 45Msps, Full-Duplex

Analog Front-End

________________________________________________________________

Maxim Integrated Products

19-0529; Rev 1; 9/06

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART* PIN-PACKAGE PKG CODE

MAX19713ETN 56 Thin QFN-EP** T5677-1

MAX19713ETN+ 56 Thin QFN-EP** T5677-1

All devices are specified over the -40°C to +85°C operating range.

EP = Exposed paddle.

Denotes lead-free package.

Functional Diagram and Selector Guide appear at end of

data sheet.

TOP VIEW

MAX19713

THIN QFN

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

OGND

DA0

DA1

DA2

DA3

REFN

COM

REFIN

QDP

QDN

GND

IDP

IDN

DAC1

DAC2

DAC3

ADC1

1 2 3 4 5 6 7 8 9 1011121314

42 41 40 39 38 37 36 35 34 33 32 31 30 29

GND

AD0

AD1

QAP

QAN

GND

CLK

GND

IAN

IAP

REFP

DA6

DA5

DA4

DA7

DA8

DA9

DOUT

DIN

SCLK

GND

ADC2

EXPOSED PADDLE (GND)

CS/WAKE

NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.

Pin Configuration

WiMAX CPEs

801.11a/b/g WLAN

VoIP Terminals

Portable Communication

Equipment

Summary of content (37 pages)

PAGE 1
9-0529; Rev 1; 9/06 KIT ATION EVALU E L B AVAILA 10-Bit, 45Msps, Full-Duplex Analog Front-End Applications WiMAX CPEs 801.11a/b/g WLAN Portable Communication Equipment VoIP Terminals ♦ Three 12-Bit, 1µs Aux-DACs ♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging ♦ Excellent Gain/Phase Match ±0.03° Phase, ±0.02dB Gain (Rx ADC) at fIN = 5.
PAGE 2
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND ...........-0.3V to (VDD + 0.
PAGE 3
10-Bit, 45Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 5
10-Bit, 45Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 6
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
10-Bit, 45Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 8
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 9
10-Bit, 45Msps, Full-Duplex Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 10
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.
PAGE 11
10-Bit, 45Msps, Full-Duplex Analog Front-End 70 56.0 60 55.0 SNR (dB) 55.5 55 QA IA 45 57.0 56.0 QA 55.5 54.5 54.0 IA 53.5 54.5 54.0 53.5 53.0 53.0 35 52.5 52.5 30 52.0 -15 -20 -10 0 -5 52.0 5 10 15 ANALOG INPUT AMPLITUDE (dBFS) 20 25 30 35 40 45 20 25 fIN = 13.
PAGE 12
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) 40 45 50 55 60 QA MAX19713 toc22 60 10 35 TEMPERATURE (°C) Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs.
PAGE 13
10-Bit, 45Msps, Full-Duplex Analog Front-End Tx DAC CHANNEL-QD TWO-TONE SPECTRAL PLOT -30 -40 -50 -60 -50 -80 -80 25 20 -90 15 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 5 FREQUENCY (MHz) 15 20 25 30 35 40 45 Tx DAC INTEGRAL NONLINEARITY 0.8 MAX19713 toc32 1.0 MAX19713 toc31 10 SAMPLING FREQUENCY (MHz) Rx ADC DIFFERENTIAL NONLINEARITY Rx ADC INTEGRAL NONLINEARITY 1.50 1.25 1.00 0.75 30 -60 FREQUENCY (MHz) 0.8 0.6 0.6 0.4 0.4 0.
PAGE 14
Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) AUX-ADC INTEGRAL NONLINEARITY AUX-DAC DIFFERENTIAL NONLINEARITY 0.8 0.6 1.0 0.4 0.5 0.2 INL (LSB) DNL (LSB) MAX19713 toc38 1.
PAGE 15
10-Bit, 45Msps, Full-Duplex Analog Front-End PIN NAME FUNCTION 1 REFP Positive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. 2, 8, 11, 39, 41, 47, 51 VDD Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IAP Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP. 4 IAN Channel-IA Negative Analog Input.
PAGE 16
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End The MAX19713 integrates three 12-bit auxiliary DACs (aux-DACs) and a 10-bit, 333ksps auxiliary ADC (auxADC) with 4:1 input multiplexer. The aux-DAC channels feature 1µs settling time for fast AGC, VGA, and AFC level setting. The aux-ADC features data averaging to reduce processor overhead and a selectable clockdivider to program the conversion rate. MAX19713 operates from a single 2.7V to 3.3V analog supply and a 1.8V to 3.3V digital supply.
PAGE 17
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713 Table 1. Rx ADC Output Codes vs.
PAGE 18
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End 5.5 CLOCK-CYCLE LATENCY (QA) 5 CLOCK-CYCLE LATENCY (IA) IA QA tCLK tCL tCH CLK tDOQ D0–D9 tDOI D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q Figure 3. Rx ADC System Timing Diagram Table 2. Tx DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.
PAGE 19
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713 MAX19713 EXAMPLE: Tx DAC CH-ID Tx RFIC INPUT REQUIREMENTS • DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (TYP) 0° • BASEBAND INPUT = ±400mV DC-COUPLED 90° Tx DAC CH-QD FULL SCALE = 1.26V COMMON-MODE LEVEL VCOMD = 1.06V SELECT CM1 = 0, CM0 = 0 VCOMD = 1.06V VFS = ±400mV ZERO SCALE = 0.86V 0V Figure 4.
PAGE 20
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End Tx DAC Timing Figure 5 shows the relationship among the clock, input data, and analog outputs. Channel ID data is latched on the falling edge of the clock signal, and channel QD data is latched on the rising edge of the clock signal, at which point both ID and QD outputs are simultaneously updated.
PAGE 21
10-Bit, 45Msps, Full-Duplex Analog Front-End D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB) ENABLE-16 E11 = 0 Reserved E10 = 0 Reserved E9 — — E6 E5 E4 — E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0
PAGE 22
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End Table 5. MAX19713 Tx, Rx, and FD Control Using SPI Commands ADDRESS A3 A2 A1 DATA BITS A0 E2 0 1 0000 (16-Bit Mode) and 1000 (8-Bit Mode) 1 1 1 E1 1 0 0 1 1 E0 1 0 1 0 1 MODE SPI1-Rx SPI2-Tx FUNCTION (Tx-Rx SWITCHING SPEED) DESCRIPTION COMMENT SLOW Rx Mode: Rx ADC = ON Rx Bus = Enabled Tx DAC = OFF (Tx DAC outputs at 0V) Tx Bus = OFF (all inputs are pulled high) Slow transition to Tx mode from this mode. Low power.
PAGE 23
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713 Table 6. MAX19713 Default (Power-On) Register Settings REGISTER NAME D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 (MSB) 15 14 13 12 11 10 9 8 7 6 5 0 0 0 1 1 1 0 0 Aux-ADC = ON — — 0 1 1 0 1 0 ENABLE-16 Aux-DAC1 Aux-DAC1 to Aux-DAC3 = ON 0 0 — FD mode 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1 output set to 1.
PAGE 24
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End Table 9.
PAGE 25
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713 tCSW CS/WAKE tCSS tCP tCS SCLK tCH tDS DIN tCL tDH MSB LSB Figure 6. Serial-Interface Timing Diagram CS/WAKE SCLK DIN 16-BIT SERIAL DATA INPUT ADC DIGITAL OUTPUT SINAD SETTLES TO WITHIN 1dB AD0–AD9 tWAKE,SD,ST_ TO Rx MODE OR tENABLE,RX DAC ANALOG OUTPUT SETTLES TO 10 LSB ERROR ID/QD tWAKE,SD,ST_ TO Tx MODE OR tENABLE,TX Figure 7.
PAGE 26
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End System Clock Input (CLK) Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns).
PAGE 27
10-Bit, 45Msps, Full-Duplex Analog Front-End AD0 SELECTION Table 16. Auxiliary ADC Clock (CLK) Divider 0 Aux-ADC Idle (Default) AD9 AD8 AD7 Aux-ADC CONVERSION CLOCK 1 Aux-ADC Start-Convert 0 0 0 CLK Divided by 1 (Default) 0 0 1 CLK Divided by 2 0 1 0 CLK Divided by 4 0 1 1 CLK Divided by 8 1 0 0 CLK Divided by 16 1 0 1 CLK Divided by 32 1 1 0 CLK Divided by 64 1 1 1 CLK Divided by 128 Table 13. Auxiliary ADC Reference AD1 SELECTION 0 Internal 2.
PAGE 28
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End The fastest method to perform sequential conversions with the aux-ADC is by sending consecutive commands setting AD10 = 1, AD0 = 1. With this sequence the CS/WAKE falling edge shifts data from the previous conversion on to DOUT and the rising edge of CS/WAKE loads the next conversion command at DIN. Allow enough time for each conversion to complete before sending the next conversion command. See Figure 8 for single and continuous conversion examples.
PAGE 29
10-Bit, 45Msps, Full-Duplex Analog Front-End 25Ω IAP 0.1μF 22pF VIN COM 0.33μF 0.1μF IAN 25Ω 22pF MAX19713 25Ω 0.1μF Reference Configurations The MAX19713 features an internal precision 1.024Vbandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 18). In internal reference mode, connect REFIN to V DD . VREF is an internally generated 0.
PAGE 30
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 10 shows an RF transformer converting the MAX19713 Tx DAC differential analog outputs to single-ended. IDP VOUT Using Op-Amp Coupling Drive the MAX19713 Rx ADC with op amps when a balun transformer is not available. Figures 11 and 12 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications.
PAGE 31
10-Bit, 45Msps, Full-Duplex Analog Front-End MAX19713 R4 600Ω R5 600Ω RISO 22Ω R1 600Ω IAN CIN 5pF MAX19713 R2 600Ω R3 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM RISO 22Ω CIN 5pF R10 600Ω IAP R11 600Ω Figure 12. Rx ADC DC-Coupled Differential Drive capacitor in parallel with a 2.2µF capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33µF ceramic capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
PAGE 32
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End VDD = 2.7V TO 3.3V OVDD = 1.8V TO VDD DATA MUX AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 DATA MUX DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 IAP 10-BIT ADC IAN QAP 10-BIT ADC FDD ZIF TRANSCEIVER QAN IDP 10-BIT DAC IDN QDP AGC 10-BIT DAC QDN SYSTEM CLOCK PROGRAMMABLE OFFSET/CM DAC1 12-BIT AUX-DAC TCXO DAC2 SERIAL INTERFACE AND SYSTEM CONTROL 12-BIT AUX-DAC DAC3 CLK CS/WAKE SCLK DIN DOUT 1.
PAGE 33
10-Bit, 45Msps, Full-Duplex Analog Front-End DAC Offset Error Offset error (Figure 14a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming. ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale.
PAGE 34
MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself.
PAGE 35
10-Bit, 45Msps, Full-Duplex Analog Front-End VDD = 2.7V TO 3.3V IAP OVDD = 1.8V TO VDD DATA MUX AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 DATA MUX DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 SYSTEM CLOCK CLK 10-BIT ADC IAN QAP 10-BIT ADC QAN IDP 10-BIT DAC IDN QDP 10-BIT DAC QDN PROGRAMMABLE OFFSET/CM DAC1 12-BIT AUX-DAC DAC2 12-BIT AUX-DAC SERIAL INTERFACE AND SYSTEM CONTROL DOUT 1.
PAGE 36
Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX19713 10-Bit, 45Msps, Full-Duplex Analog Front-End (NE-1) X e E/2 k e D/2 C L (ND-1) X e D D2 D2/2 b L E2/2 C L k E2 C L C L L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.
PAGE 37
10-Bit, 45Msps, Full-Duplex Analog Front-End PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 F 2 2 Revision History Pages changed at Rev 1: 1–4, 29, 37 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.