Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX2309ETI+

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General Description

The MAX2306/MAX2308/MAX2309 are IF receivers

designed for dual-band, dual-mode, and single-mode

N-CDMA and W-CDMA cellular phone systems. The

signal path consists of a variable-gain amplifier (VGA)

and I/Q demodulator. The devices feature guaranteed

+2.7V operation, a gain control range of over 110dB,

and high input IP3 (-31dBm at 35dB gain, 3.4dBm at

-35dB gain).

Unlike similar devices, the MAX2306 family of receivers

includes dual oscillators and synthesizers to form a

self-contained IF subsystem. The synthesizer’s refer-

ence and RF dividers are fully programmable through a

3-wire serial bus, enabling dual-band system architec-

tures using any common reference and IF frequency.

The differential baseband outputs have enough band-

width to suit both N-CDMA and W-CDMA systems, and

offer saturated output levels of 2.7Vp-p at a low +2.75V

supply voltage. Including the low-noise voltage-con-

trolled oscillator (VCO) and synthesizer, the MAX2306

draws only 26mA from a +2.75V supply in CDMA (dif-

ferential IF) mode.

The MAX2306/MAX2308/MAX2309 are available in 28-

pin Thin QFN and QFN packages.

Applications

Single/Dual/Triple-Mode CDMA Handsets

Globalstar Dual-Mode Handsets

Wireless Data Links

W-CDMA Handsets

Wireless Local Loop (WLL)

Features

♦ Complete IF Subsystem Includes VCO and

Synthesizer

♦ Supports Dual-Band, Triple-Mode Operation

♦ VGA with >110dB Gain Control

♦ Quadrature Demodulator

♦ High Output Level (2.7V)

♦ Programmable Charge-Pump Current

♦ Supports Any IF Frequency Between 40MHz and

300MHz

♦ 3-Wire Programmable Interface

♦ Low Supply Voltage (+2.7V)

MAX2306/MAX2308/MAX2309

CDMA IF VGAs and I/Q Demodulators

with VCO and Synthesizer

________________________________________________________________ Maxim Integrated Products 1

19-2014; Rev 3; 8/04

EVALUATION KIT AVAILABLE

Pin Configurations appear at end of data sheet.

Block Diagram appears at end of data sheet.

Ordering Information

Selector Guide

*Exposed paddle

PART

TEMP RANGE

PIN-PACKAGE

MAX2306EGI

-40°C to +85°C

28 QFN-EP*

MAX2306ETI

-40°C to +85°C

28 TQFN-EP*

MAX2308EGI

-40°C to +85°C

28 QFN-EP*

MAX2308ETI

-40°C to +85°C

28 TQFN-EP*

MAX2309EGI

-40°C to +85°C

28 QFN-EP*

MAX2309ETI

-40°C to +85°C

28 TQFN-EP*

PART MODE DESCRIPTION INPUT RANGE

MAX2306

AMPS,

Cellular CDMA,

PCS CDMA

Dual Band, Triple Mode with Two

IF VCOs

40MHz to 300MHz

MAX2308

AMPS,

Cellular CDMA,

PCS CDMA

Dual Band, Triple Mode with Common

IF VCO

70MHz to 300MHz

MAX2309

External AMPS,

Cellular CDMA,

PCS CDMA

Dual Band, Triple Mode (Drives External

AMPS Discriminator)

70MHz to 300MHz

Summary of content (20 pages)

PAGE 1
9-2014; Rev 3; 8/04 ILABLE N KIT AVA EVALUATIO CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain control range of over 110dB, and high input IP3 (-31dBm at 35dB gain, 3.4dBm at -35dB gain).
PAGE 2
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer ABSOLUTE MAXIMUM RATINGS Digital Input Current SHDN, MODE, DIVSEL, BUFEN, DATA, CLK, EN, STBY .....................................±10mA Continuous Power Dissipation (TA = +70°C) 28-Pin QFN (derate 28.5mW/°C above TA = +70°C) ...........2W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ..........
PAGE 3
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer (MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.
PAGE 4
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer AC ELECTRICAL CHARACTERISTICS (continued) (MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.
PAGE 5
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer RECEIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE 25.00 TA = -40°C 22.50 0.010 TA = +25°C 0.006 3.5 4.0 4.5 5.0 2.5 3.0 GAIN vs. INPUT FREQUENCY 3.5 4.0 4.5 5.0 5.5 0.5 60.0 59.5 40 35 30 59.0 58.0 20 56.5 500 MAX2306/8/9 toc07 7.4 2 4 6 8 10 12 14 16 18 20 7.0 40 6.8 NF (dB) TA = +25°C -30 -60 -40 -20 0 20 40 60 FREQUENCY (MHz) GAIN (dB) NOISE FIGURE vs. TEMPERATURE VCO VOLTAGE vs.
PAGE 6
Typical Operating Characteristics (continued) (MAX2306/MAX2308/MAX2309 EV kits, VCC = +2.75V, registers set to default power-up states, fIN = 183.7MHz, fREF = 19.2MHz, synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA = +25°C, unless otherwise noted.) IF PORT PARALLEL RESISTANCE vs. FREQUENCY IF PORT PARALLEL CAPACITANCE vs.
PAGE 7
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer PIN NAME FUNCTION MAX2306 MAX2308 MAX2309 1, 28 — — TANKL+, TANKL- — 1, 4 — N.C. 2, 3 2, 3 1, 2 TANKH+, TANKH- Differential Tank Input for High-Frequency Oscillator — — 3 BUFEN LO Buffer Amplifier—active low 4 — — MODE Mode Select. High selects CDMA mode; low selects FM mode. — — 4 LOOUT Internal VCO Output.
PAGE 8
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Pin Description (continued) PIN NAME FUNCTION MAX2306 MAX2308 MAX2309 25 25 25 BYP 26 26 26 CP_OUT 27 27 27 GND Ground — 28 21 N.C. No Connection — — 28 DIVSEL Exposed Paddle EP Bypass Node. Must be capacitively decoupled (bypassed) to ground. Charge-Pump Output High selects M1/R1; low selects M2/R2.
PAGE 9
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309 47pF 0.01µF VCC 2.4kΩ 0.01µF 0.068µF 0.1µF BYP BYP 0.01µF BYP CP_OUT 33pF 10kΩ 0.01µF FM- GND FM FM+ TANKL+ CDMA+ 33nH 2pF 10kΩ 33pF 10kΩ 33pF MAX2306 CDMA 680Ω TANKLCDMATANKH+ DAC VGC 47pF 33nH 2pF VCC 33pF 10kΩ TANKHVCC MODE VCC VCC 47pF DATA 3-WIRE EN GND CLK REF SHDN IOUT+ I QOUT+ 10kΩ 10kΩ IOUT- Q QOUTLOCK 47kΩ VCC Figure 1.
PAGE 10
Table 1.
PAGE 11
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer M CONTROLS REGISTER B OPERATIONAL MODE ACTION RESULT CP_POL TEST_EN TURBOCHARGE DIVSEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY SHDN L S B TEST_MODE M S B SHDN P I N SHUTDOWN Shutdown pin completely shuts down chip L X X X X X X X X X X X X X SHUTDOWN 0 in shutdown register bit leaves serial port active H X X X X X X X X X X X X L 0 in standby pin turns off VGA and modulator only H 0 0
PAGE 12
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 47pF 2.4kΩ 0.01µF 0.01µF BYP BYP VCC 0.01µF 0.068µF 0.01µF MAX2308 CP_OUT 0.01µF GND 33pF 10kΩ VCC BYP FM- TANKH+ FM+ 2pF 33nH FM CDMA+ 33pF 10kΩ TANKH- CDMA 680Ω CDMAVGC VCC VCC VCC GND DATA REF EN DAC 47pF 47pF SHDN I_OUT+ VCC 3-WIRE CLK Q_OUT+ 10kΩ 10kΩ I_OUT- Q Q_OUTLOCK 47kΩ VCC Figure 2.
PAGE 13
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer M S B L S B DIVSEL BUFEN STBY TEST_MODE CP_POL TES_TEN TURBOCHARGE DIVSEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY SHDN CONTROL REGISTER SHDN PINS SHUTDOWN Shutdown pin completely powers down the chip L X X X X X X X X X X X X X X X X SHUTDOWN 0 in shutdown register bit leaves serial bus active H X X X X X X X X X X X X X X X 0 STANDBY 0 in standby pin turns off VGA and modulator o
PAGE 14
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer 47pF 0.068µF 0.01µF 2.4kΩ 0.01µF BYP BYP CP_OUT BYP VCC 0.01µF 0.01µF GND TANKH+ 2pF BUFEN DISCRIMINATOR LOOUT VCC GND REF SHDN IOUT+ I DAC VGC 47pF VCC VCC DATA 3-WIRE EN CLK QOUT+ 10kΩ 10kΩ IOUT- FM CDMA- VCC 47pF LIMITER CDMA 680Ω MAX2309 TANKH- 455kHz CDMA+ 33nH 33pF 10kΩ STBY DIVSEL 33pF 10kΩ VCC QOUTLOCK 47kΩ VCC Figure 3.
PAGE 15
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309 VCC 800µA D1 R1 TANK_- TANK_+ RL RB CF RB RE RL CF RE Figure 4. Voltage-Controlled Oscillators VCO_H 14-BIT M1 COUNTER (00) DATA CPI CLK EN START BIT M U X (010) 16-BIT DATA/ADDRESS REGISTER 2-BIT CP1 11-BIT R1 COUNTER 2-BIT CP2 11-BIT R2 COUNTER FREF (011) (11X) CPOUT 13-BIT CONTROL REGISTER CP2 (01) VCO_L 14-BIT M2 COUNTER Figure 5.
PAGE 16
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MSB DATA LSB *SB *START BIT MUST BE LOGIC HIGH. CLK RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. EN Figure 6. 3-Wire Interface Timing Diagram Table 4. Control Register, Default State: 0B57h, Address: 110b BIT ID BIT NAME POWERUP STATE BIT LOCATION 0 = LSB TM TEST_MODE 0 12 Must be 0 for normal operation.
PAGE 17
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer START BIT SHIFT REGISTER 1 A2/M0 A1 A0 A2/M0 A1 A0 M1 REGISTER M113 M1/0 0 0 M2 REGISTER M213 M2/0 0 1 CP1 AND R1 REGISTERS CP1/1 CP1/0 R1/10 R1/0 0 1 0 CP2 AND R2 REGISTERS CP2/1 CP2/0 R2/10 R2/0 0 1 1 SD 1 1 0 CTRL REGISTER /1 TM POL TE TC DS VB VS BD BE FT IS SB DATA Figure 7. Programming Logic Table 6. Charge-Pump Control Bits Table 5.
PAGE 18
MAX2306/MAX2308/MAX2309 CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer Functional Diagram MAX2306 MAX2308 MAX2309 CDMA+ VGC CDMA- IOUT+ IOUT- EN CLK DATA LOGIC SB 1 SHIFT REGISTER MAX2306 MAX2308 ÷2 FM+ QOUT+ FM- 2 2 CP1 R1 REGISTER CP2 R2 REGISTER 010 11 011 FT 14 11 MAX2309 01 M2 REGISTER DIVSEL M1 REGISTER QOUT- 14 00 MAX2306 MODE IS VS TM POL TE DS TC VB VS BD BE FT IS SB SD 110 DS VCO_L CONTROL 2 2 11 14 11 14 TANKL+ 2 TANKL- 14 11 R C
PAGE 19
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer DAC VCC QOUT+ QOUT- LOCK AVCC BYP BYP FM- FM+ CDMA+ CDMA- VGA DATA EN VCC CLK 0 90 /2 MAX2306 /M CHARGE PUMP PHASE DETECTOR /R BYP AGND TANKL+ TANKH+ TANKH- REF MODE DVCC SHDN IOUT+ IOUT- CP_OUT TANKL- ______________________________________________________________________________________ 19 MAX2306/MAX2308/MAX2309 Block Diagram
PAGE 20
Pin Configurations BYP BYP BYP FM- 25 24 23 22 FM- 22 CP_OUT BYP 23 26 BYP 24 GND BYP 25 N.C. CP_OUT 26 27 GND 27 28 TANKL- 28 TOP VIEW TANKL+ 1 21 FM+ N.C. 1 21 FM+ TANKH+ 2 20 CDMA+ TANKH+ 2 20 CDMA+ TANKH- 3 19 CDMA- TANKH- 3 19 CDMA- MODE 4 18 VGC N.C.