Datasheet

MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
10Maxim Integrated
Pin Description
Pin Configuration
PIN NAME FUNCTION
1 CLK
Serial Clock Input. The data is latched into the 32-bit shift register on the rising edge of the
CLK line.
2 DATA Serial Data Input. The serial data is loaded MSB first. The 3 LSBs identify the register address.
3 LE
Load Enable Input. When LE goes high the data stored in the shift register is loaded into the
appropriate latches.
4 CE
Chip Enable. A logic-low powers the part down and the charge pump becomes high
impedance.
5 SW Fast-Lock Switch. Connect to the loop filter when using the fast-lock mode.
6 VCC_CP Power Supply for Charge Pump. Place decoupling capacitors as close as possible to the pin.
7 CP_OUT Charge-Pump Output. Connect to external loop filter input.
8 GND_CP Ground for Charge-Pump. Connect to board ground, not to the paddle.
9 GND_PLL Ground for PLL. Connect to main board ground plane, not to the paddle.
10 VCC_PLL Power Supply for PLL. Place decoupling capacitors as close as possible to the pin.
11 GND_RF Ground for RF Outputs. Connect to board ground plane, not to the paddle.
12 RFOUTA_P Open Collector Positive RF Output A. Connect to supply through RF choke or 50I load.
13 RFOUTA_N Open Collector Negative RF Output A. Connect to supply through RF choke or 50I load.
MAX2870
TQFN
TOP VIEW
29
30
28
27
12
11
13
DATA
CE
SW
V
CC_CP
CP_OUT
14
CLK
BIAS_FILT GND_TUNE TUNE REG NOISE_FILT GND_VCO
12
V
CC_DIG
4567
2324 22 20 19 18
REF_IN
MUX_OUT
RFOUTB_P
RFOUTA_N
RFOUTA_P
GND_RF
LE
RSET
3
21
31
10
GND_SD
EP
V
CC_PLL
32
9
V
DD_SD
GND_PLL
+
GND_DIG
26
15
RFOUTB_N
RFOUT_EN
25
16
V
CC_RF
GND_CP
V
CC_VCO
8
17
LD