Datasheet

MAX2870

23.5MHz to 6000MHz Fractional/

Integer-N Synthesizer/VCO

12Maxim Integrated

Detailed Description

4-Wire Serial Interface

The MAX2870 serial interface contains five write-only and

one read-only 32-bit registers. The 29 most-significant

bits (MSBs) are data, and the three least-significant bits

(LSBs) are the register address. Register data is loaded

MSB first through the 4-wire serial interface (SPI). When

LE is logic-low, the logic level at DATA is shifted at the

rising edge of CLK. At the rising edge of LE, the 29 data

bits are latched into the register selected by the address

bits. The user must program all register values after

power-up.

0x04, 0x03, 0x02, 0x01, and 0x00. Several bits are dou-

ble buffered to update the settings at the same time. See

the register descriptions for double buffered settings.

Upon power-up, all registers should be programmed

twice with at least a 20ms pause between writes. The first

write ensures that the device is enabled, and the second

write starts the VCO selection process.

The user must set MUX = 1100. To begin the read

sequence, set LE to logic-low, send 32 periods of CLK,

and set LE to logic-high. While the CLK is running, the

DATA pin can be held at logic-high or logic-low for 29

clocks, but the last 3 bits must be 110 to indicate regis-

ter 6. Then finally, send 1 period of the clock. The MSB

of register 0x06 appears on the falling edge of the next

clock and continues to shift out for the next 29 clock

cycles (Figure 2). After the LSB of register 0x06 has

been read, the user can reset MUX = 0000.

Figure 1. SPI Timing Diagram

Figure 2. Initiating Readback

CLK

DATA

3130291 33 34 35

DON’T CARE

MUX_OUT

LEH

CLK

DATA

BIT31 BIT30 BIT29 BIT1 BIT0

LES

LEW