Datasheet
MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
13Maxim Integrated
Power Modes
The MAX2870 can be put into low-power mode by set-
ting SHDN = 1 (register 2, bit 5) or by setting the CE pin
to logic-low.
After exiting low-power mode, allow at least 20ms for
external capacitors to charge to their final values before
programming the final VCO frequency.
Reference Input
The reference input stage is configured as a CMOS
inverter with shunt resistance from input to output. In
shutdown mode this input is set to high impedance to
prevent loading of the reference source.
The reference input signal path also includes optional x2
and ÷2 blocks. When the reference doubler is enabled
(DBR = 1), the maximum reference input frequency is lim-
ited to 100MHz. When the doubler is disabled, the refer-
ence input frequency is limited to 200MHz. The minimum
reference frequency is 10MHz. The minimum R counter
divide ratio is 1, and the maximum divide ratio is 1023.
Int, Frac, Mod, and R Counter
Relationship
The phase-detector frequency is determined as follows:
f
PFD
= f
REF
O [(1 + DBR)/(R x (1 + RDIV2))]
f
REF
represents the external reference input frequency.
DBR (register 2, bit 25) sets the f
REF
input frequency
doubler mode (0 or 1). RDIV2 (register 2, bit 24) sets
the
f
REF
divide-by-2 mode (0 or 1). R (register 2,
bits 23:14) is the value of the 10-bit programmable
reference
counter
(1 to 1023). The maximum f
PFD
is
50MHz for frac-N mode and 105MHz for int-N mode.
The
R-divider can be held in reset when RST (register 2,
bit 3) = 1.
The VCO frequency (f
VCO
), N, F, and M can be deter-
mined based on desired RF output frequency (f
RFOUTA
)
as follows:
Set DIVA value property based on f
RFOUTA
and DIVA
register table (register 4[22.20])
f
VCO
= f
RFOUTA
x DIVA
If bit FB = 1, (DIVA is not in PLL feedback loop):
N + (F/M) = f
VCO/
f
PFD
If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA
≤ 16:
N + (F/M) = (f
VCO
/f
PFD
)/DIVA
If bit FB = 0, (DIVA is in PLL feedback loop) and DIVA > 16:
N + (F/M) = (f
VCO /
f
PFD)/16
N is the value of the 16-bit N counter (16 to 65535),
programmable through bits 30:15 of register 0. M is the
fractional modulus value (2 to 4095), programmable
through bits 14:3 of register 1. F is the fractional division
value (0 to MOD - 1), programmable through bits 14:3 of
register 0. In frac-N mode, the minimum N value is 19 and
maximum N value is 4091. The N counter is held in reset
when RST = 1 (register 2, bit 3). DIVA is the RF output
divider setting (0 to 7), programmable through bits 22:20
of register 4. The division ratio is set by 2
DIVA
.
The RF B output frequency is determined as follows:
If BDIV = 0 (register 4, bit 9), f
RFOUTB
= f
RFOUTA
.
If BDIV = 1, f
RFOUTB
= f
VCO
.
Int-N/Frac-N Modes
Integer-N mode is selected by setting bit INT = 1 (regis-
ter 0, bit 31). When operating in integer-N mode, it is also
necessary to set bit LDF (register 2, bit 8) to set the lock
detect to integer-N mode.
The device’s frac-N mode is selected by setting bit INT = 0
(register 0, bit 31). Additionally, set bit LDF = 0 (register
2, bit 8) for frac-N lock-detect mode.
If the device is in frac-N mode, it will remain in frac-N
mode when fractional division value F = 0, which can
result in unwanted spurs. To avoid this condition, the
device can automatically switch to integer-N mode when
F = 0 if the bit F01 = 1 (register 5, bit 24).
Phase Detector and Charge Pump
The device’s charge-pump current is determined by the
value of the resistor from pin RSET to ground and the
value of bits CP (register 2, bits 12:9) as follows:
I
CP
= 1.63/R
SET
x (1 + CP)
Figure 3. Reference Input
REF_IN
X2
DIVIDE-BY-2
PFD
R COUNTER
MUXMUX