Datasheet

MAX2870
23.5MHz to 6000MHz Fractional/
Integer-N Synthesizer/VCO
14Maxim Integrated
To reduce spurious in frac-N mode, set charge-pump
linearity bit CPL = 1 (register 1, bits 30:29). For int-N
mode, set CPL = 0. For lower noise operation in int-N
mode, set charge-pump output clamp bit CPOC = 1
(register 1, bit 31) to prevent leakage current onto the
loop filter. For frac-N mode, set CPOC = 0.
The charge-pump output can be put into high-imped-
ance mode when TRI = 1 (register 2, bit 4). The output is
in normal mode when TRI = 0.
The phase detector polarity can be changed if an active
inverting loop filter topology is used. For noninverting
loop filters, set PDP = 1 (register 2, bit 6). For inverting
loop filters, set PDP = 0.
MUX_OUT and Lock Detect
MUX_OUT is a multipurpose test output for observing
various internal functions of the MAX2870. MUX_OUT
can also be configured as serial data output. Bits MUX
(register 2, bit 28:26) are used to select the desired
MUX_OUT signal (see Table 6).
Lock detect can be monitored through the LD output by
setting the LD bits (register 5, bits 23:22). For digital lock
detect, set LD = 01. The digital lock detect is dependent
on the mode of the synthesizer. In frac-N mode set LDF
= 0, and in int-N mode set LDF = 1. To set the accuracy
of the digital lock detect, see Tables 1 and 2.
Analog lock detect can be set with LD = 10. In this mode,
LD is an open-drain output and requires an external
pullup resistor.
The lock detect output validity is dependent on many
factors. The lock detect output is not valid during the
VCO auto selection process. After the VCO auto selec-
tion process has completed, the lock detect output is not
valid until the TUNE voltage has settled. TUNE voltage
settling time is dependent on loop filter bandwidth, and
can be calculated using the EE-Sim Simulation tool found
at www.maximintegrated.com.
Fast-Lock
The device uses a fast-lock mode to decrease lock time.
This mode requires that CP = 0000 (register 2, bits 12:9)
and that the shunt resistive portion of the loop filter be
segmented into two parts, where one resistor is 1/4th
the total resistance, and the other resistor is 3/4th the
total resistance. The larger resistor should be connected
from ground to SW, and the smaller resistor from SW to
the loop filter capacitor. When CDM = 01 (register 3, bits
16:15), fast-lock is active after the VAS has completed.
During fast-lock, the charge pump is increased to CP =
1111 and the shunt loop filter resistance is set to 1/4th
the total resistance by changing pin SW from high imped-
ance to ground. Fast-lock deactivates after a timeout set
by the user. This timeout is loop filter dependent, and is
set by:
t
FAST-LOCK
= M x CDIV/f
PFD
where M is the modulus setting and CDIV is the clock
divider setting. The user must determine the CDIV setting
based on their loop filter time constant.
RFOUTA± and RFOUTB±
The device has dual differential open-collector RF out-
puts that require an external RF choke 50I resistor to
supply for each output. Each differential output can
be independently enabled or disabled by setting bits
Table 2. Int-N Digital Lock-Detect Settings
Table 1. Frac-N Digital Lock-Detect Settings
PFD FREQUENCY LDS LDP
LOCKED UP/DOWN
TIME SKEW (ns)
NUMBER OF LOCKED
CYCLES TO SET LD
UP/DOWNTIME SKEW
TO UNSET LD (ns)
P 32MHz
0 0 10 5 15
P 32MHz
0 1 6 5 15
> 32MHz 1 X 4 5 4
PFD FREQUENCY LDS LDP
LOCKED UP/DOWN
TIME SKEW (ns)
NUMBER OF LOCKED
CYCLES TO SET LD
UP/DOWNTIME SKEW
TO UNSET LD (ns)
P 32MHz
0 0 10 40 15
P 32MHz
0 1 6 40 15
> 32MHz 1 X 4 40 4